FDSOI Transistor Back-Bias Layout for Low-Leakage MLC Driving
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Solution Overview
Problem
Existing resistive memory technologies face challenges in increasing passing current while limiting current leakage, which is necessary for effective multi-level cell (MLC) programming, particularly in fully depleted silicon-on-insulator (FDSOI) architectures, and require complex circuit modifications for analog voltage management.
Innovation Solution
A transistor driving device with uniformly conductive transistors, such as NMOS, uses a single bias voltage for forward or reverse back-biasing, combined with a second well for dynamic isolation, allowing extended bias voltage ranges and reduced current leakage, facilitating MLC programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional driving circuits are used for FDSOI transistors, then the transistor can be driven, but the control of the transistor's conductivity type is limited and cannot be dynamically switched
Solution Approach 1:
The driving device is divided into multiple independent cells (first cells and second cells) with different conductivity types. Each cell can be independently controlled through separate biasing circuits, allowing the transistor to switch between different conductivity types by activating specific cells. This segmentation enables dynamic adaptability without requiring a complete circuit redesign.
Solution Approach 2:
The biasing circuit is designed to provide multiple bias voltages (first bias voltage and second bias voltage) that can control different cells with different conductivity types. This multi-functional biasing approach allows a single circuit structure to support both N-type and P-type transistor operation, achieving versatility in conductivity control.
2Speed
If standard driving methods are used, then the circuit implementation is straightforward, but the switching speed and response time are insufficient
Solution Approach 1:
The device pre-configures multiple cells with different conductivity types and their corresponding biasing circuits in advance. When switching is needed, the system can immediately activate the appropriate cell and apply the corresponding bias voltage without requiring time-consuming reconfiguration or regeneration of the driving circuit, thus achieving fast switching speed and reduced response time.
3Productivity
If FDSOI transistors are driven without optimized biasing, then the basic function is maintained, but the performance and efficiency are suboptimal
Solution Approach 1:
The biasing circuit dynamically adjusts the bias voltages applied to different cells based on the required transistor operation mode. By optimizing the bias voltage levels for each conductivity type and cell configuration, the system achieves optimal transistor performance and efficiency while minimizing energy consumption through adaptive biasing rather than fixed suboptimal biasing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances transistor performance and reduces current leakage, enabling efficient MLC programming and memory cell size reduction with improved energy efficiency and simplified circuit design.
Implementation Method 1
a channel configured to operate in a so-called fully depleted mode, in the blocked state of the transistor
Implementation Method 2
applying, for example, a single first bias voltage in a FBB 'forward back bias' configuration via the bias circuit
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
The invention relates to a transistor driving device (1) FDSOI comprising: - A plurality of first cells (21, 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h) having a first type of conductivity (P), each first cell (21) being associated with a group of transistors (20), - At least one second cell (22, 22a, 22b, 22c, 22d) having a second type of conductivity (N), formed under and around the first cells (21), - A biasing circuit configured to apply at least one first bias voltage V1 to the first cells (21), and at least one second bias voltage V2 to at least one second cell (22). Advantageously, all the transistors (20) have the second type of conductivity (N). The invention also relates to a method for driving the preceding device.