Clock Tree Cell Integration in 28nm FDSOI Standard Cells
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Solution Overview
Problem
In 28nm FDSOI technology, integrating a clock tree cell within a circuit comprising standard cells with different threshold voltages is challenging due to space constraints, as current design rules require large spacing between cells to prevent electrical interference, leading to significant area loss and reduced logic element density.
Innovation Solution
The clock tree cell is integrated within a block of standard cells using a single semiconductor box surrounded by a semiconductor strip with opposite doping, forming a reverse-biased p-n junction for electrical insulation, reducing the required area and allowing independent electrical control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large spacing is maintained between clock tree cell and standard cells to prevent electrical interference, then electrical insulation is improved, but area occupied increases significantly
Solution Approach 1:
A semiconductor strip with opposite doping type is introduced as an intermediary element between the clock tree cell and adjacent standard cells. This strip forms reverse-biased p-n junctions at its interfaces, creating an electrical barrier that prevents interference while allowing compact integration. The intermediary strip acts as a localized isolation structure that replaces the need for large spacing.
Solution Approach 2:
The doping type parameter of the semiconductor strip is changed to be opposite to that of the adjacent cells. This parameter change creates reverse-biased p-n junctions that provide electrical insulation. By controlling the doping concentration and type, the isolation effectiveness is optimized while minimizing the spatial footprint of the isolation structure.
2Quantity of substance
If clock tree cell is integrated within standard cell block, then logic element density is improved, but electrical interference between cells increases
Solution Approach 1:
The semiconductor strip divides the continuous semiconductor region into electrically isolated segments. By inserting this oppositely-doped strip between the clock tree cell and standard cells, the structure is segmented into distinct electrical domains. This segmentation allows multiple logic elements to be integrated closely while preventing harmful electrical interactions through the reverse-biased junctions created by the segmentation.
3Object-generated harmful factors
If reverse-biased p-n junction is used for electrical insulation, then leakage current is reduced, but manufacturing complexity increases
Solution Approach 1:
The semiconductor strip is fabricated using the same semiconductor material and processing steps as the adjacent cells, maintaining material homogeneity. The opposite doping type is achieved through standard doping processes that are already part of the CMOS fabrication sequence. This approach reduces manufacturing complexity by using homogeneous materials and existing process steps, rather than introducing exotic materials or complex isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes the area occupied by the clock tree cell, reduces leakage currents, and enables more efficient use of space, allowing for a higher density of logic elements without compromising electrical insulation or performance.
Implementation Method 1
surrounded by a semiconductor strip with opposite doping, forming a reverse-biased p-n junction for electrical insulation
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
The invention relates to an integrated circuit, comprising - a block comprising: • a first (38) and a second (40) semiconductor cells of opposite doping; • standard cells (42, 43), placed side by side, each standard cell (42) comprising first transistors (60, 62); a clock shaft cell (30), surrounded by the standard cells, the clock shaft cell (30) comprising: - a third semiconductor cell (104), having a doping of the same type as the doping of the first cell (38); - second transistors (100, 102); - a semiconductor strip (106), extending continuously around the third cell (104) and having a doping of the opposite type to the doping of the third cell, to electrically isolate the third cell (104) from the first cell (38).