FDSOI Contact Lateral Extensions for Leakage Prevention
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Solution Overview
Problem
In fully depleted silicon-on-insulator (FDSOI) technology, the miniaturization of transistors leads to smaller contact areas for source and drain regions, making it challenging to form contacts without introducing defects like divots in shallow trench insulator regions, which can result in high field leakage and punch-through defects.
Innovation Solution
A method is developed to form contacts with upper lateral extensions that extend over shallow trench insulator regions, allowing for reliable contact formation with raised source and drain regions while avoiding divots, using a silicide source/drain contact layer and interlayer dielectric stack, and connecting to a power rail spine for improved contact reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact areas are reduced to increase circuit density, then device integration is improved, but manufacturing precision deteriorates due to difficulty in forming contacts without defects
Solution Approach 1:
The contact structure is extended into the lateral dimension by forming upper lateral extensions that protrude from the contact opening and extend over the shallow trench insulator region. This dimensional change allows the contact to achieve sufficient area for reliable electrical connection while maintaining a small footprint on the semiconductor layer, thereby resolving the contradiction between high circuit density and manufacturable contact precision.
Solution Approach 2:
The contact structure is segmented into multiple functional parts: a contact opening through the interlayer dielectric stack, and upper lateral extensions that protrude laterally. This segmentation allows the vertical contact path to remain small for high density while the lateral extensions provide the necessary contact area for reliable manufacturing, thus resolving the precision-density contradiction.
2Ease of manufacture
If contacts are formed directly over raised source/drain regions, then alignment is simplified, but reliability deteriorates due to divot formation in shallow trench insulator regions
Solution Approach 1:
The upper lateral extensions act as an intermediary structure that bridges the contact opening and the shallow trench insulator region. The extensions extend over the STI region without requiring the contact opening itself to overlap the STI boundary, thus maintaining alignment simplicity while avoiding divot formation and improving reliability.
Solution Approach 2:
The contact structure utilizes the lateral dimension by forming extensions that protrude from the contact opening. This allows the contact to achieve reliable electrical connection while the contact opening remains properly aligned with the raised source/drain region, avoiding the divot formation issue without compromising alignment ease.
3Productivity
If critical dimensions are reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to increased difficulty in contact formation
Solution Approach 1:
The contact structure is extended into the lateral dimension with upper lateral extensions that protrude from the contact opening. This dimensional change allows the critical vertical dimensions to be reduced for high device density while the lateral extensions provide sufficient contact area, thereby maintaining manufacturable precision even as critical dimensions are reduced.
Solution Approach 2:
The contact is segmented into a small contact opening for high density and larger upper lateral extensions for reliable electrical connection. This segmentation allows the critical dimensions of the contact opening to be reduced for increased device density while the extensions maintain the necessary contact quality for manufacturable precision.
Data Source
AI summary
A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.