FDSOI Dielectric Stack for Uniform Thin Silicon Top Layers
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Solution Overview
Problem
Conventional FDSOI processes face challenges in achieving uniformity, defectivity, and surface roughness of the silicon top layer due to thinning, dewetting, and difficulty in increasing anneal temperatures, leading to unstable thickness and weakened bond strength.
Innovation Solution
The method involves implanting ions into a donor structure to form a cleave plane, bonding with a handle structure using a dielectric layer of hafnia, zirconia, or alumina, and performing a cleaving process to form a silicon-on-insulator structure, followed by a smoothing anneal and cleaning to achieve a silicon top layer thickness of less than 15 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional thinning methods are used to reduce silicon top layer thickness, then the desired thin thickness is achieved, but thickness uniformity degrades
Solution Approach 1:
A cleave plane is formed at a predetermined depth within the silicon top layer through ion implantation before the actual thinning process. This preliminary action creates a controlled separation plane that enables precise thickness control during subsequent mechanical cleaving, achieving both thin thickness and high uniformity
2Shape
If argon or hydrogen smoothing process is used to reduce surface roughness, then surface smoothness is improved, but dewetting occurs causing local thickness increase
Solution Approach 1:
The patent changes the chemical composition parameter of the dielectric layer from conventional materials to hafnia, zirconia, or alumina. This material substitution fundamentally alters the bonding characteristics at the silicon-dielectric interface, preventing dewetting during high-temperature annealing while still enabling effective surface smoothing
3Shape
If anneal temperature is increased to reduce surface roughness, then surface smoothness improves, but dewetting is caused due to SiO evaporation
Solution Approach 1:
The dielectric layer material is changed from SiO2 to hafnia, zirconia, or alumina, which have higher thermal stability and lower vapor pressure. This parameter change allows annealing at higher temperatures to achieve surface smoothing without the dewetting problem caused by SiO evaporation in conventional processes
4Device complexity
If dielectric layer thickness is kept at 20 nm as in conventional processes, then process simplicity is maintained, but bond strength is weakened due to gas accumulation at the bond interface
Solution Approach 1:
The dielectric layer thickness parameter is increased from the conventional 20 nm to at least 50 nm. This thicker dielectric layer provides sufficient volume to absorb and diffuse gases that accumulate during bonding and annealing processes, preventing bond interface degradation and maintaining strong adhesion between silicon and handle structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances silicon top layer uniformity, reduces defectivity, and improves surface roughness while maintaining reasonable yield and throughput by using thicker dielectric layers and higher anneal temperatures, preventing dewetting and strengthening the bond.
Implementation Method 1
Ions are implanted into a donor structure to form a cleave plane in the donor structure
Implementation Method 2
The silicon-on-insulator structure is annealed to smooth the silicon top layer and form a smoothed silicon-on-insulator structure
Data Source
AI summary
Fully-depleted silicon-on-insulator structures and methods for preparing fully-depleted silicon-on-insulator structures. The fully-depleted silicon-on-insulator structure may include a top layer, a handle structure and a dielectric layer disposed between the silicon top layer and handle structure. The dielectric layer of the silicon-on-insulator structure may be composed of hafnia, zirconia, alumina, or combinations thereof. In some embodiments, the dielectric layer is relatively thick such as at least 20 nm or even at least 50 nm.