FDSOI Self-Aligned Diffusion Break for Leakage Isolation
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Solution Overview
Problem
Current CMOS devices face challenges with electrostatic isolation in silicon-on-insulator (SOI) structures, leading to increased leakage and device degradation due to channel uni-axial strain loss and complexity in manufacturing processes.
Innovation Solution
A method involving oxygen ion implantation and annealing within a self-aligned dummy gate recess in a fully depleted silicon-on-insulator (FDSOI) device to form an oxidized isolation area, reducing leakage and enhancing device performance by creating a physical break between source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy gates are used for electrostatic isolation in SOI structures, then isolation between active devices is achieved, but leakage increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the isolation region by forming an oxidized layer through oxygen ion implantation and annealing. This transforms the electrical properties of the SOI layer in the isolation area, creating a depleted region that provides electrostatic isolation without the leakage problems associated with conventional dummy gates.
Solution Approach 2:
The patent employs oxygen ion implantation followed by annealing to accelerate oxidation in the isolation region. This creates a highly oxidized layer that effectively isolates adjacent active devices electrostatically while avoiding the leakage issues of traditional isolation methods.
2Manufacturing precision
If two independent patterning sequences are used to define active regions, then precise patterning is achieved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent merges the isolation formation process with the existing gate patterning process. By forming the oxidized isolation regions using the same lithography and etching steps that define the gate patterns, the need for separate independent patterning sequences is eliminated, reducing manufacturing complexity while maintaining precision.
Solution Approach 2:
The patent makes the gate patterning process multi-functional by having it simultaneously define both the gate structures and the isolation regions. This universal approach eliminates the need for dedicated isolation patterning steps, reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage and increases device performance by providing effective physical isolation between gate structures, allowing for different voltage controls and reducing the overall structure footprint, while being independent of lithography-dependent diffusion break sizes.
Implementation Method 1
implanting oxygen ions into the recess
Implementation Method 2
annealing the SOI layer within the recess to form an isolation area
Data Source
AI summary
Disclosed herein are approaches for forming a FDSOI, single diffusion break device. In one approach, a method may include providing a plurality of gates in a stack of layers, wherein each gate of the plurality of gates comprises a sidewall spacer, and forming a mask over the stack of layers, wherein an opening through the mask exposes a dummy gate of the plurality of gates. The method may further comprise etching a gate material of the dummy gate to form a recess in a silicon-on-insulator (SOI) layer of the stack of layers, implanting oxygen ions into the recess, and annealing the SOI layer within the recess to form an isolation area.