Floating Gate Flash Memory Integration in FDSOI Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of flash memory devices in CMOS technologies, particularly in Fully Depleted Silicon-On-Insulator (FDSOI) manufacturing techniques, requires additional deposition and masking steps, increasing the complexity and cost of the process flow for forming field effect transistors (FETs).
Innovation Solution
A method is developed to integrate flash memory devices within the FDSOI process flow by forming a silicon-on-insulator (SOI) substrate with a buried insulation layer, removing the semiconductor layer and buried insulation from a memory area to expose the bulk substrate, and then forming a dielectric layer, floating gate, and control gate, ensuring the floating gate's surface is at the same height as the logic area, thereby simplifying the process and reducing the number of processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memory devices are integrated in FDSOI manufacturing techniques, then memory functionality is achieved, but the number of deposition and masking steps increases
Solution Approach 1:
The patent divides the substrate into distinct logic areas and memory areas, allowing different processing sequences for each region. The memory area undergoes selective removal of the semiconductor layer and buried insulation to expose the bulk substrate, while the logic area retains the full FDSOI structure. This segmentation enables parallel processing paths that reduce overall complexity.
Solution Approach 2:
The patent performs preliminary removal of the semiconductor layer and buried insulation layer in the memory area before forming the flash memory structure. By preparing the bulk substrate surface in advance, subsequent steps for forming the dielectric layer, floating gate, and control gate can proceed without additional masking operations, thereby reducing the total number of processing steps.
2Adaptability or versatility
If additional deposition and masking steps are added, then flash memory integration is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the flash memory fabrication process with the existing FDSOI transistor manufacturing flow by utilizing the same bulk substrate and integrating memory formation steps into the logic device process sequence. The control gate and floating gate structures are formed using similar deposition techniques as the logic transistors, allowing combined processing that reduces manufacturing cost.
3Device complexity
If the floating gate surface is at the same height as the logic area, then process simplification is achieved, but structural precision requirements increase
Solution Approach 1:
The patent forms the floating gate structure such that its upper surface is at the same height level as the logic area surface, creating an equipotential surface that simplifies subsequent processing steps. This height alignment eliminates the need for additional planarization or height-matching operations, as the floating gate naturally integrates with the logic device surface level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of manufacturing by integrating flash memory devices with FDSOI transistor devices using a simplified process flow, maintaining the physical state of memory elements and enhancing capacitive coupling for efficient data storage.
Implementation Method 1
The floating gate uses channel hot electrons for writing from the drain and tunneling for erasure from the source
Implementation Method 2
The floating gate uses channel hot electrons for writing from the drain and tunneling for erasure from the source
Implementation Method 3
The control gate 14 and the floating gate 13 are separated from each other by an isolation layer 19, for example, an oxide-nitride-oxide (ONO) layer provided in order to enhance the capacitive coupling between the floating gate 13 and the control gate 14
Data Source
AI summary
A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.