FDSOI Transistor Threshold Voltage Control via Ground Plane Biasing
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Solution Overview
Problem
Integrated circuits in FDSOI technology face challenges in achieving distinct threshold voltages for nMOS and pMOS transistors due to the low doping level of the channel, which limits the differentiation of threshold voltages and results in threshold voltage distortions and mismatched leakage and conduction currents.
Innovation Solution
The use of a buried insulating layer with specific doping levels and biases for the ground planes, combined with a gate metal work function difference of 70 meV, allows for the control of threshold voltages, enabling balanced threshold voltages and homogeneous leakage and conduction currents for nMOS and pMOS transistors of the same level, without requiring different biasing voltages or additional fabrication complexities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the channel doping level is differentiated to achieve distinct threshold voltages for nMOS and pMOS transistors, then the threshold voltage control is improved, but the manufacturing precision deteriorates because the channel doping level in FDSOI technology is almost zero and cannot exhibit significant variations
Solution Approach 1:
The patent changes the control parameter from channel doping level to ground plane doping level and electrical bias. By adjusting the doping concentration and bias voltage of the ground planes, the threshold voltage of nMOS and pMOS transistors can be differentiated despite the channel doping being nearly zero in FDSOI technology
Solution Approach 2:
The ground planes act as an intermediary element between the substrate and the transistor channels. By controlling the ground plane properties (doping and bias), the patent indirectly controls the threshold voltage of the transistors, bypassing the limitation of zero channel doping
2Manufacturing precision
If electrically biased ground planes are used to achieve distinct threshold voltages, then the threshold voltage differentiation is improved, but the device complexity increases due to additional doping and biasing requirements
Solution Approach 1:
The patent merges the threshold voltage control function into the ground plane structure itself. By doping the ground planes and applying electrical biases, both nMOS and pMOS threshold voltages are controlled through a single structural element (the ground planes) rather than requiring separate control mechanisms for each transistor type
Solution Approach 2:
The ground planes serve multiple functions: they provide electrical biasing, control threshold voltages for both nMOS and pMOS transistors, and enable differentiation of threshold voltages across multiple transistor levels (LVT, RVT, HVT) within the same integrated circuit structure
3Productivity
If threshold voltages are differentiated for high-speed and low-power logic gates, then the circuit performance is improved, but the threshold voltage distortion and mismatch between nMOS and pMOS transistors increases
Solution Approach 1:
The patent applies local quality by differentiating the ground plane doping levels and biases for specific transistor regions. nMOS transistors receive p-type ground plane doping with specific biases, while pMOS transistors receive n-type ground plane doping with different biases, creating locally optimized threshold voltages that maintain proper matching between complementary transistor pairs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces threshold voltage discrepancies between nMOS and pMOS transistors to 70 mV, achieving balanced threshold voltages and consistent current characteristics for LVT and RVT transistors, enhancing the flexibility and performance of the integrated circuit without complicating the fabrication process.
Implementation Method 1
By altering the doping of the ground planes and their electrical bias, it is possible to improve the electrostatic control of these transistors, thereby making it possible to define various ranges of threshold voltages for these transistors
Implementation Method 2
The use of a buried insulating layer with specific doping levels and biases for the ground planes, combined with a gate metal work function difference of 70 meV, allows for the control of threshold voltages
Data Source
AI summary
The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg−0.04−0.005*Xge<Wf1<Wfmg−0.03−0.005*Xge.