FDSOI IC Double Isolation Mask Cost Reduction
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Solution Overview
Problem
The high cost of masks used in standard-cell architecture with double STI-DTI isolation in fully depleted silicon-on-insulator (FDSOI) technology is a significant challenge, primarily due to the need for aggressive and relaxed patterns in shallow-trench-isolation and deep-trench-isolation masks.
Innovation Solution
The implementation of a silicon-on-insulator substrate with deep trench isolation for the majority of transistors and shallow trench isolations on the edges, where the deep trench isolation mask cost is aggressive and the shallow isolation mask cost is relaxed, reducing the overall mask cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double STI-DTI isolation is used in standard-cell architecture, then effective isolation and transistor performance are maintained, but mask cost increases due to aggressive and relaxed patterns
Solution Approach 1:
The patent merges the isolation functions of STI and DTI into a unified DTI structure. The deep trench isolation simultaneously provides both the deep isolation (replacing STI) and the shallow isolation (through its upper portion), eliminating the need for separate STI and DTI masks while maintaining effective isolation between transistors and between rows.
Solution Approach 2:
The deep trench isolation structure serves multiple functions: it provides deep isolation between complementary transistors (replacing STI function), provides shallow isolation between rows (replacing DTI function), and enables a single mask pattern that is less aggressive than both previous masks, thereby reducing mask cost while maintaining isolation effectiveness.
2Manufacturing precision
If aggressive pattern is used for STI mask, then precise isolation between adjacent transistors is achieved, but mask cost increases
Solution Approach 1:
The patent combines the STI and DTI isolation functions into a single DTI structure with unified dimensions. The DTI trench width is set to 100 nm, which provides sufficient isolation precision without requiring the aggressive 72 nm pattern of STI, thereby reducing mask cost while maintaining manufacturing precision.
3Reliability
If standard pattern is used for DTI mask, then isolation between rows is achieved, but mask cost increases when combined with aggressive STI mask
Solution Approach 1:
The patent merges row isolation and transistor isolation functions into a single DTI structure. The 100 nm DTI trench width provides sufficient isolation between rows without requiring a separate STI mask, eliminating the need to pay for both standard and aggressive masks simultaneously.
Solution Approach 2:
The deep trench isolation structure serves dual purposes: it provides deep isolation between complementary transistors within a row and shallow isolation between adjacent rows. This multi-functionality allows a single mask to replace both the aggressive STI mask and the standard DTI mask, reducing total mask cost.
Data Source
AI summary
A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.