FDSOI Semiconductor Layer Thickness Control via Local Etching
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Solution Overview
Problem
Current methods for producing semiconductor layers with different thicknesses, such as those used in FDSOI technology, face challenges in precisely controlling the thickness and uniformity of the buried oxide layer, leading to variability in transistor threshold voltage and reduced integration density.
Innovation Solution
A method involving local etching of a semiconductor layer to create regions of different thicknesses, followed by oxidation and partial removal of the oxide to form a continuous insulation layer, allowing for the formation of a semiconductor layer with precise and uniform thicknesses, enabling abrupt junctions and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If localised implantation of oxygen through a mask and annealing is used to thicken the BOX layer at certain areas, then different thicknesses of silicon can be defined above different thicknesses of the BOX layer, but precise control of the BOX layer thickness in the thickened areas becomes very tricky and poor uniformity of thickness is found
Solution Approach 1:
The patent replaces the mechanical/chemical process of localised ion implantation and annealing with a purely physical etching process. Instead of adding material to thicken the BOX layer locally, the invention removes semiconductor material locally to create thickness variations, thereby avoiding the control and uniformity issues associated with localised implantation.
Solution Approach 2:
The patent inverts the conventional approach: rather than creating thickness variations in the BOX layer and having silicon thickness follow from it, the method creates thickness variations directly in the silicon layer by localised etching, then uses oxidation to form a continuous BOX layer that adapts to the silicon topography.
2Shape
If localised implantation of oxygen is used to form the BOX layer with different thicknesses, then the profile of the passage from thick area to thin area of the buried oxide layer is not sufficiently abrupt, but this increases the minimum separation of devices and reduces integration density
Solution Approach 1:
The patent replaces the gradual diffusion-based thickening process with a controlled etching process that creates sharp, well-defined boundaries. The localised etching followed by oxidation produces abrupt transitions between thick and thin regions, enabling closer device spacing and higher integration density.
3Reliability
If FDSOI technology is used to eliminate random dopant fluctuation, then variability from RDF is reduced, but a new source of variability is introduced because the thickness TSi of the silicon layer may vary from one device to another and affect threshold voltage
Solution Approach 1:
The patent applies local quality by creating regions with different silicon layer thicknesses on the same wafer. Logic transistor regions receive thin silicon layers for high performance, while analogue transistor regions receive thick silicon layers for stability and matching. This local differentiation allows each transistor type to operate in its optimal thickness regime.
Solution Approach 2:
The patent segments the wafer into distinct regions with different silicon thicknesses. By dividing the wafer surface into logic regions and analogue regions with appropriately different thicknesses, the method enables co-integration of transistor types with different thickness requirements, reducing variability within each segment.
4Manufacturing precision
If the thickness TSi of the silicon layer is made finer to improve transistor performance, then threshold voltage control is improved, but threshold voltage fluctuates more and variability increases
Solution Approach 1:
The patent applies local quality by creating regions with different silicon layer thicknesses on the same wafer. Logic transistor regions receive thin silicon layers for high performance, while analogue transistor regions receive thick silicon layers for stability and matching. This local differentiation allows each transistor type to operate in its optimal thickness regime.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the precise control of semiconductor layer thickness, reducing defects and variability, and enabling the co-integration of different types of transistors on the same wafer with improved integration density and flat surface profiles.
Implementation Method 1
local etching of the first semiconductor layer so that the first semiconductor layer remains continuous and comprises at least one first region the thickness (tSi1) of which is less than the thickness (tSi2) of at least one second region; the local etching thus forms at least one cavity in the first semiconductor layer
Implementation Method 2
oxidation of the first semiconductor layer in order to form a film of electrically insulating oxide on the surface of the first semiconductor layer so that, in the first region, the film of oxide extends as far as the insulating layer of the initial stack
Data Source
AI summary
A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.