Single Diffusion Break Device for FDSOI Leakage Reduction
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Solution Overview
Problem
Current semiconductor designs face challenges with increased leakage due to the need for dummy gates, which restrict voltage types to single drains and lead to device degradation, especially in reducing critical dimensions and stress after etching in SOI processes.
Innovation Solution
A single diffusion break structure is implemented using a channel oxidation process with a nitride fill material, providing physical isolation between adjacent gate structures and reducing leakage by forming an oxidized region within the dummy gate structure, allowing multiple voltage types and preventing stress loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy gates are used to provide isolation between active devices, then physical isolation is achieved, but overall leakage increases
Solution Approach 1:
The patent changes the physical-chemical state of the dummy gate channel material by oxidizing it to form silicon dioxide. This parameter change transforms the conductive semiconductor material into an insulating oxide, thereby eliminating leakage while maintaining the physical isolation function of the dummy gate structure
Solution Approach 2:
The patent converts the harmful leakage effect into a beneficial isolation effect by oxidizing the dummy gate channel. The oxidation process transforms the dummy gate from a potential leakage source into an effective isolation structure that prevents leakage between adjacent active devices
2Reliability
If dummy gates are used to provide isolation, then physical isolation is achieved, but only single voltage type can be applied to drains
Solution Approach 1:
By oxidizing the dummy gate channel to create an insulating barrier, the patent enables independent voltage control of adjacent drains. The oxidation creates sufficient isolation to allow different voltage types (e.g., positive and negative voltages) to be applied to drains of adjacent devices without interference
3Productivity
If critical dimensions are reduced to increase integration density, then more transistor elements can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs a self-aligned oxidation process where the dummy gate structure itself serves as the mask for oxidation. This self-service approach automatically ensures precise alignment and consistent oxidation depth, reducing manufacturing complexity and improving precision at reduced critical dimensions
Solution Approach 2:
The dummy gate structure is formed in advance before the oxidation process. This preliminary action establishes the precise location and dimensions of the future isolation region, enabling subsequent oxidation to occur at the exact desired position with high precision
4Ease of manufacture
If etching processes are used in SOI fabrication, then device structures are formed, but stress loss occurs causing device degradation
Solution Approach 1:
The patent converts the harmful stress loss from etching into a beneficial outcome by performing oxidation instead. The oxidation process forms the isolation structure without the stress-inducing mechanical removal of material, thereby preventing device degradation while achieving the necessary structural isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces overall leakage, enhances scaling, increases contact overlap, and prevents device degradation by enabling different voltage controls and maintaining performance without stress loss in the semiconductor devices.
Implementation Method 1
oxidizing the exposed fully depleted semiconductor on insulator material within the channel region of the dummy gate structure to form a physical isolation structure between diffusions of the active gate structure
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.