FDSOI Mixed-Threshold Layout With Flexible Back Biasing
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Solution Overview
Problem
Current fully depleted semiconductor-on-insulator chip structures face increased chip area consumption and reduced design flexibility due to physical separation of well areas and limitations on back biasing, which restricts the use of mixed threshold voltage transistors and forward/reverse back biasing options.
Innovation Solution
An area-efficient fully depleted semiconductor-on-insulator structure with mixed threshold voltage transistors and both forward and reverse back biasing options, incorporating a buried Nwell and multiple well regions with electrically connected bias voltages to allow for mixed threshold voltage transistors and flexible biasing configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If physical separation between regular well and flip well areas is implemented, then back biasing control is simplified, but chip area consumption increases
Solution Approach 1:
The patent merges the regular well area and flip well area into a single integrated well structure, eliminating the need for physical separation. This allows both LVT and HVT transistors to coexist in the same well area, reducing chip area while maintaining the ability to apply different back biasing voltages to different transistor types through selective well region doping and gate control mechanisms
2Ease of manufacture
If all transistors use the same threshold voltage type (LVT or HVT), then manufacturing process is simplified, but design flexibility is reduced
Solution Approach 1:
The patent applies local quality by creating different doped regions within the same well structure. Specifically, it uses selectively doped source/drain regions and extension regions with different doping concentrations to achieve different threshold voltages for NFETs and PFETs locally, while maintaining a unified manufacturing process for the overall well structure
Solution Approach 2:
The patent implements dynamic threshold voltage control through adjustable back biasing mechanisms. By applying different voltages to the well regions and utilizing configurable doping profiles, the threshold voltage of transistors can be dynamically adjusted between LVT and HVT states, providing design flexibility without requiring separate manufacturing processes
Data Source
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AI summary
Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.