FDSOI Devices with Multiple Threshold Voltages via Fixed Charge Regions
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Solution Overview
Problem
Current semiconductor technologies face challenges in efficiently integrating multiple threshold voltage transistors within the same integrated circuit, as existing methods fail to effectively manage power consumption and performance across different types of field effect transistors (FETs) due to limitations in achieving distinct threshold voltage levels.
Innovation Solution
The method involves fabricating fully depleted silicon on insulator (FDSOI) devices with multiple threshold voltages by introducing fixed charges to the interface of an insulating layer and a semiconductor substrate using ion implantation, allowing for the creation of devices with ultra-high, high, low, and ultra-low threshold voltage levels by varying the type and configuration of dopants and fixed charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple threshold voltage transistors are integrated within the same integrated circuit, then power consumption is optimized and performance is enhanced, but existing fabrication methods fail to achieve distinct threshold voltage levels
Solution Approach 1:
The patent applies local quality by introducing fixed charge regions at specific locations within the transistor structure, particularly at the interface between the insulating layer and semiconductor substrate. By concentrating fixed charges in specific regions rather than uniformly distributing them, the invention achieves distinct threshold voltage levels in different transistor areas while maintaining overall integration. This localized charge introduction enables precise control over threshold voltage characteristics in different parts of the same integrated circuit.
Solution Approach 2:
The invention utilizes parameter changes by varying the concentration, sign, and spatial distribution of fixed charges to achieve different threshold voltage levels. By adjusting parameters such as fixed charge density (positive or negative), implantation energy, and regional distribution, the patent creates transistors with ultra-high, high, low, and ultra-low threshold voltages from the same base structure. This parameter variation approach enables multi-threshold voltage integration without requiring fundamentally different device architectures.
2Manufacturing precision
If fixed charges are introduced to the interface of insulating layer and semiconductor substrate, then precise control over threshold voltage levels is achieved, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by introducing fixed charges during the insulating layer formation process or immediately thereafter, before completing the full transistor fabrication sequence. By performing the charge introduction step early in the process flow, the invention integrates threshold voltage control into the base fabrication sequence rather than requiring separate, complex post-processing steps. This timing strategy reduces overall process complexity while achieving precise threshold voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of FDSOI devices with precise control over threshold voltage levels, optimizing power consumption and performance by allowing for the use of high and low power FETs in the same integrated circuit, enhancing their application in various critical and non-critical paths.
Implementation Method 1
introducing fixed charges to the interface of an insulating layer and a semiconductor substrate using ion implantation
Data Source
AI summary
Methods of fabricating devices (e.g., FDSOI devices) having multiple threshold voltages are described. One method includes providing a first fixed charge region proximate to an interface of an insulating (e.g., buried oxide (BOX) layer) and a semiconductor substrate for a first device. The first charge region has a first configuration of fixed charges. The method also includes providing a second fixed charge region proximate to the interface of the insulating layer and the semiconductor substrate for the second device. The second charge region has a second configuration of fixed charges that is different than the first configuration.