Compact FDSOI OTP-MTP Cell Structure for Program Disturb Reduction
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Solution Overview
Problem
Current memory designs for semiconductor devices face challenges in forming compact one-time programmable (OTP) and multiple-time programmable (MTP) cells, particularly in alleviating program disturb issues while maintaining a reduced cell size, especially in FDSOI and FinFET architectures.
Innovation Solution
The method involves forming a silicon-on-insulator (SOI) region or fin over a buried oxide layer, with laterally separated gate stacks having oxide/high-k layers and polysilicon or metal gate layers, along with spacers and source/drain regions, to create a compact OTP/MTP cell structure that utilizes the gates as word lines and connects a bit line to the source/drain contact, without requiring additional masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p+ implant is introduced to address program disturb in 28 nm OTP technology, then program disturb is alleviated, but cell size increases and becomes less desirable
Solution Approach 1:
The patent changes the doping parameter from p+ to n+ in the drain region, and adjusts the oxide thickness parameter to 5-15nm. These parameter changes enable program disturb immunity without requiring additional implant steps that would increase cell size, thus resolving the contradiction between reliability improvement and area minimization
2Power
If field enhancement on fin corners is utilized in 16 nm MTP technology, then set voltage and reset current are reduced, but cell size reduction is still desirable
Solution Approach 1:
The patent applies different doping types to different regions: n+ doping in the source region and p+ doping in the drain region. This local quality differentiation optimizes the field enhancement effect at fin corners for low power operation while maintaining compact cell dimensions, resolving the contradiction between power reduction and area minimization
3Reliability
If gate stacks are formed with oxide/high-k layers and polysilicon or metal gate layers, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate stack formation into distinct layers: oxide layer (5-15nm), high-k layer, and polysilicon or metal gate layer. This segmentation allows each layer to be optimized independently for performance while using standard semiconductor manufacturing processes, thus improving device performance without excessive manufacturing complexity
Data Source
AI summary
Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.