FDSOI PMOS SiGe Etching to Reduce Epitaxial Substrate Loss
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Solution Overview
Problem
The existing method for fabricating fully depleted silicon-on-insulator PMOS devices results in significant loss of the SiGe substrate due to etching steps, leading to reduced epitaxial growth and performance issues, as the presence of photo resist reduces the etch selectivity ratio of SiN to SiGe, causing about 50% increase in SiGe loss during epitaxial hard mask etching.
Innovation Solution
Combining the etching steps for the spacer dielectric layer and epitaxial hard mask into a single step, with partial etching of the epitaxial hard mask followed by in-situ photo resist stripping and continued etching of the remaining spacer dielectric layer, effectively reducing the accumulative loss of the SiGe substrate and improving epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photo resist is used in the epitaxial hard mask etching process, then the etching process can be performed, but the etch selectivity ratio of SiN to SiGe is reduced, causing about 50% increase in SiGe loss
Solution Approach 1:
The patent extracts and removes the photo resist material from the etching process by using an alternative masking approach. The epitaxial hard mask layer itself is used as the mask without requiring photo resist, thereby eliminating the harmful interaction between photo resist and SiGe that causes excessive etching and material loss.
Solution Approach 2:
The patent introduces an intermediary solution by using the epitaxial hard mask layer as a self-sufficient masking structure. This intermediary layer serves both as the etch mask and as the structural element that protects SiGe from excessive etching, replacing the need for photo resist as the masking intermediary.
2Ease of manufacture
If two etching steps are performed on spacers and epitaxial hard masks, then the mask structures can be removed, but about 34% of SiGe is lost after spacer etching and the remaining SiGe is almost completely lost after epitaxial hard mask etching
Solution Approach 1:
The patent merges the spacer etching and epitaxial hard mask etching into a single combined etching step. By using the epitaxial hard mask as the mask for both operations simultaneously, the process eliminates the need for sequential etching steps, thereby preventing the cumulative SiGe loss that occurs when two separate etching steps are performed.
Solution Approach 2:
The patent performs preliminary action by designing the epitaxial hard mask structure to serve dual purposes before etching begins. The mask is configured to protect both the spacer and the SiGe region in advance, ensuring that when etching occurs, both structures are removed in one step without exposing SiGe to repeated etching attacks.
3Manufacturing precision
If cumulative SiGe loss is reduced, then epitaxial growth in PMOS regions is improved, but the fabrication process requires modified etching steps
Solution Approach 1:
The patent applies parameter changes by modifying the etching process parameters and mask configuration to achieve single-step etching. The epitaxial hard mask thickness, composition, and structural design are adjusted to enable it to function as an effective mask for both spacer and SiGe etching in one operation, thereby reducing SiGe loss while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces SiGe substrate loss from 75 Å to 17 Å, an improvement of 77.3%, enhancing the epitaxial growth and performance of PMOS devices by minimizing the loss caused by the reduced etch selectivity ratio.
Implementation Method 1
etching to the SiGe layer 12 by using the hard mask oxide layer 16 as a mask to form a PMOS gate stack structure
Implementation Method 2
performing in-situ photo resist strip
Data Source
AI summary
The present application discloses a method for fabricating fully depleted silicon-on-insulator PMOS devices, the method includes sequentially forming a polysilicon layer and a hard mask oxide layer on an FDSOI substrate structure; etching to a SiGe layer by using the hard mask oxide layer as a mask to form a PMOS gate stack structure; sequentially depositing a spacer dielectric layer and an epitaxial hard mask; performing photolithography and etching to remove the epitaxial hard mask above the PMOS gate stack and thin the spacer dielectric layer; performing in situ photo resist strip; and etching to remove a residual spacer dielectric layer above the PMOS gate and on its surrounding substrate. The present application can effectively reduce the accumulative loss of a SiGe substrate after the epitaxial hard mask etching, improving the epitaxial growth of PMOS regions and ensuring the performance of the fabricated fully depleted silicon-on-insulator PMOS devices.