FDSOI Power-Gating Circuit Using Back-Gate Threshold Control
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Solution Overview
Problem
Conventional power gating techniques in integrated circuits require separate sleep transistors, leading to increased complexity, area overhead, and thermal issues due to the interdependence of power and thermal effects, as well as additional wiring that causes voltage variations and delay penalties.
Innovation Solution
The use of fully depleted silicon-on-insulator (FDSOI) transistors with a double-gate structure, where the back gate controller dynamically sets the threshold voltage, eliminating the need for separate sleep transistors and allowing the same transistors to perform both logic and sleep functions, thereby simplifying power gating and reducing thermal effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If separate sleep transistors are used for power gating, then leakage power is reduced, but device complexity and area overhead increase
Solution Approach 1:
The patent combines the sleep transistor and logic transistor into a single integrated device structure. The sleep transistor is formed by isolating a portion of the logic transistor channel through a first isolation structure, while the logic transistor uses a second isolation structure. This merging eliminates separate discrete sleep transistors, reducing device complexity and area overhead while maintaining power gating functionality to reduce leakage power.
Solution Approach 2:
The integrated transistor structure serves dual functions: it operates as a logic transistor during active mode and as a sleep transistor during standby mode. The same physical structure performs both logic computation and power gating functions, eliminating the need for separate dedicated sleep transistors and reducing overall device complexity.
2Loss of energy
If separate sleep transistors are used for power gating, then leakage power is reduced, but area overhead increases
Solution Approach 1:
The patent merges the sleep transistor and logic transistor into a single integrated structure where the sleep transistor is formed by a first isolation structure within the channel region of the logic transistor. This integration eliminates the need for separate discrete sleep transistor devices and their associated wiring, significantly reducing area overhead while maintaining effective power gating to reduce leakage power.
3Loss of energy
If high-Vt sleep transistors are used as header and footer switches, then subthreshold current leakage is reduced, but voltage variations and delay penalties occur due to additional wiring
Solution Approach 1:
The patent extracts the power gating function from separate header and footer switch transistors and integrates it directly into the logic transistor channel through isolation structures. This eliminates the additional wiring and RLC issues associated with external sleep transistors, removing the source of voltage variations and delay penalties while maintaining subthreshold leakage reduction.
Solution Approach 2:
By merging the sleep transistor functionality into the logic transistor structure itself through channel isolation, the patent eliminates the need for separate header and footer switches. This integration removes the additional interconnect wiring that causes RLC effects, voltage drops, and propagation delays, while still achieving effective subthreshold current leakage reduction.
4Loss of energy
If separate sleep transistors are used for power gating, then leakage power is reduced, but thermal effects increase due to interdependence of power and thermal effects
Solution Approach 1:
The patent integrates the sleep transistor functionality into the logic transistor structure through channel isolation, eliminating separate discrete sleep transistor devices. This integration reduces the total number of transistor interfaces and interconnect structures that generate heat, thereby reducing overall thermal effects in the circuit while maintaining effective power gating to reduce leakage power.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces area overhead, simplifies design complexity, improves power efficiency, and minimizes thermal effects by eliminating standalone sleep transistors and dynamically controlling threshold voltage to manage power consumption and leakage current.
Implementation Method 1
The back gate controller is configured to induce a bias in the back gate of the FDSOI transistor to dynamically set a threshold voltage value of the FDSOI transistor
Data Source
AI summary
Combining the functionality of sleep transistors with logic devices in power-gating circuits by utilizing fully depleted silicon-on-insulator (FDSOI) transistors. In an embodiment, a back gate of a FDSOI transistor controls the threshold voltage to eliminate the need for standalone sleep transistors.