FDSOI PTAT Current Source Back-Gate Bias Compensation
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Solution Overview
Problem
Conventional PTAT circuit architectures fail to eliminate the influence of manufacturing or structural-related variables on voltage-temperature or current-temperature profiles, and existing calibration algorithms do not successfully account for all process variables of an individual transistor, requiring substantial time and cost for implementation.
Innovation Solution
A circuit structure utilizing fully depleted semiconductor on insulator (FDSOI) transistors with back-gate terminals, coupled with current mirrors and adjustable voltage sources, to generate a current proportionate to absolute temperature and compensate for process variations by applying a selected back-gate bias voltage, thereby calibrating the PTAT current source to account for manufacturing-based variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PTAT circuit architectures are used, then temperature-dependent current generation is achieved, but process variations from manufacturing affect the current-temperature profile accuracy
Solution Approach 1:
The patent applies preliminary calibration action by measuring and storing compensation values for the PTAT current at different temperatures during manufacturing. These pre-determined compensation values are then used during operation to correct for process variations, eliminating the need for real-time adjustment and ensuring accurate current-temperature profiling despite manufacturing tolerances.
Solution Approach 2:
The patent implements feedback by using the measured PTAT current characteristics to determine compensation values that are fed back into the circuit operation. The system continuously monitors the relationship between current and temperature, uses this information to calculate appropriate compensation, and applies this compensation to maintain accurate current-temperature profiling despite process variations.
2Measurement precision
If calibration algorithms are applied to account for process variables, then transistor performance accuracy is improved, but substantial time and cost are required for implementation
Solution Approach 1:
The patent performs calibration actions preliminarily during the manufacturing process rather than during device operation or field use. By measuring and storing compensation values in advance, the system eliminates time-consuming calibration procedures that would otherwise be required during deployment, reducing both calibration time and associated costs while maintaining high transistor performance accuracy.
Solution Approach 2:
The patent enables the circuit to self-correct for process variations by using pre-stored compensation values that are automatically applied during operation. This self-service approach eliminates the need for external calibration equipment, technicians, or complex real-time adjustment mechanisms, thereby reducing both time and cost while maintaining accurate transistor performance.
3Measurement precision
If frequent recalibrations are performed to compensate for process variations, then output current accuracy is maintained, but system complexity and cost increase
Solution Approach 1:
The patent resolves this contradiction by performing all necessary calibration actions preliminarily during manufacturing and storing the results for automatic application during operation. This approach maintains high output current accuracy without requiring frequent recalibrations, complex real-time adjustment mechanisms, or additional calibration infrastructure, thereby reducing system complexity and cost while preserving measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for a single calibration to compensate for process variations, ensuring the output current is independent of temperature, supply voltage, and resistance changes, reducing the need for frequent recalibrations and minimizing costs.
Implementation Method 1
an adjustable voltage source coupled to the back-gate terminal of the at least one FDSOI transistor of the current source, wherein the adjustable voltage source applies a selected back-gate bias voltage to the back-gate terminal of the at least one FDSOI transistor to adjust the current to compensate for process variations of the device transistor
Implementation Method 2
a current source including at least one fully depleted semiconductor on insulator (FDSOI) transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure
Implementation Method 3
a first current mirror electrically coupled to the current source and a gate terminal of a device transistor, wherein the first current mirror applies a gate bias to the device transistor based on a magnitude of the current
Data Source
AI summary
The disclosure provides a circuit structure including a current source including at least one FDSOI transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure; a first current mirror electrically coupled to the current source and a gate terminal of a device transistor, wherein the first current mirror applies a gate bias to the device transistor based on a magnitude of the current, and wherein a source or drain terminal of the device transistor includes an output current of the circuit structure; and an adjustable voltage source coupled to the back-gate terminal of the at least one FDSOI transistor of the current source, wherein the adjustable voltage source applies a selected back-gate bias voltage to the back-gate terminal of the at least one FDSOI transistor to adjust the current to compensate for process variations of the device transistor.