FDSOI Transistor Biasing via Segmented STI and Conductive Plugs
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Solution Overview
Problem
Integrated circuits with FDSOI transistors face a significant biasing delay due to capacitive coupling between ground planes and wells, which is detrimental for high-frequency switching applications.
Innovation Solution
A conductive path is created between the ground plane and its well using a conductive element, reducing the biasing delay without altering the channel properties of the FDSOI transistors, and this is achieved by forming shallow trench isolations that do not reach the bottom of the wells, allowing for independent biasing and high integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shallow trench isolations are formed to provide electrical isolation between transistors, then integration density is improved, but biasing delay increases due to capacitive coupling between ground planes and wells
Solution Approach 1:
The isolation structure is segmented into two distinct parts: shallow trench isolations that provide electrical isolation between adjacent transistors, and deep conductive plugs that extend through the isolation trenches to the substrate. This segmentation allows the shallow isolations to maintain high integration density while the deep plugs provide low-impedance biasing paths that reduce capacitive coupling effects and minimize biasing delay.
Solution Approach 2:
Deep conductive plugs act as intermediary elements that connect the ground planes to the substrate through the isolation trenches. These plugs serve as low-impedance pathways that mediate the biasing process, reducing the capacitive coupling between ground planes and wells by providing alternative discharge paths, thereby reducing biasing delay without compromising the electrical isolation function of the shallow trench isolations.
2Manufacturing precision
If ground planes are placed between UTBOX layer and semiconductor well to control threshold voltage, then transistor threshold voltage control is improved, but capacitive coupling between ground planes and wells increases causing biasing delay
Solution Approach 1:
The coupling path between ground planes and wells is segmented by introducing deep conductive plugs that extend through the isolation trenches. This segmentation creates multiple low-impedance discharge paths that bypass the capacitive coupling through the UTBOX layer, allowing the ground planes to maintain their threshold voltage control function while reducing the harmful capacitive effects that cause biasing delay.
Solution Approach 2:
The solution extends the isolation structure into the vertical dimension by forming deep conductive plugs that penetrate through the isolation trenches to the substrate. This vertical extension creates additional biasing pathways in the depth dimension, providing low-impedance connections that reduce the capacitive coupling effects in the horizontal plane and minimize biasing delay while preserving threshold voltage control.
3Loss of time
If deep isolations are formed to reduce capacitive coupling, then biasing delay is reduced, but manufacturing complexity and process steps increase
Solution Approach 1:
The isolation and biasing functions are merged into a single integrated structure. The shallow trench isolations and deep conductive plugs are formed together in a unified isolation structure, where the shallow isolations provide electrical isolation between transistors and the deep plugs provide low-impedance biasing paths. This merging eliminates the need for separate complex processes and reduces overall manufacturing complexity while achieving both isolation and reduced biasing delay.
Solution Approach 2:
The dual-structure isolation system serves multiple functions simultaneously: the shallow trench isolations provide electrical isolation between adjacent transistors, while the deep conductive plugs provide low-impedance biasing paths and reduce capacitive coupling. This multi-functionality allows a single isolation structure to address both isolation requirements and biasing delay reduction without requiring additional separate structures or processes, thereby reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The conductive path significantly reduces the biasing delay between ground planes and wells, enhancing the performance of high-frequency transistors without major changes to the manufacturing process.
Implementation Method 1
A conductive path is created between the ground plane and its well using a conductive element, reducing the biasing delay
Implementation Method 2
a thin layer of silicon (typically featuring a thickness of a few nanometers) is separated from a semiconductor substrate by a relatively thick electrically insulating layer
Implementation Method 3
FDSOI (Fully Depleted Silicon On Insulator) transistors have, by design, a depleted channel, featuring a low doping level
Data Source
AI summary
An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.