FDSOI Transistor Active Layer Thickness Control via Trench Etching

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Solution Overview

Problem

The formation of transistors with different channel thicknesses on a shared substrate, such as PDSOI and FDSOI transistors, is challenging due to structural anomalies at the interfaces, leading to reliability issues and high production costs in existing methods.

Innovation Solution

A method involving the formation of isolating trenches and active regions with a difference in height, allowing for simultaneous etching to control the thickness of the active layer, reducing structural anomalies and improving the reliability of FDSOI transistors by using a masking layer and dry etching techniques to taper the active layer and isolating trench, ensuring the desired thickness and rounded edges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional methods are used to form transistors with different channel thicknesses on a shared substrate, then both PDSOI and FDSOI transistors can be integrated, but structural anomalies occur at the interfaces leading to reliability issues

Engineering Contradiction:
Improveintegration of different transistor typesVSAvoidtransistor reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming an initial displacement (negative offset) of the isolating trench relative to the active layer before the main etching process. This pre-positioning allows the subsequent etching to create the desired positive displacement and rounded edges without directly forming the trench at the final position, thereby preventing structural anomalies at the interface between the active layer and isolating trench.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If conventional etching methods are used to form isolating trenches, then the manufacturing process is simple, but structural anomalies occur at the trench interfaces

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidinterface quality
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent introduces a preliminary displacement step where the isolating trench is initially formed with a negative offset relative to the active layer. This preliminary positioning enables the etching process to proceed in a controlled manner, creating rounded edges and avoiding sharp interfaces that cause structural anomalies, while maintaining overall process simplicity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies spheroidality by ensuring that the etching process creates rounded edges at the interface between the active layer and isolating trench, rather than sharp corners. This curvature is achieved through the controlled etching of the preliminary displacement, eliminating stress concentration points and improving interface quality without complicating the manufacturing process.

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Ease of manufacture

If the isolating trench is formed at the same level as the active layer, then the manufacturing process is straightforward, but structural anomalies and reliability issues occur

Engineering Contradiction:
Improvetrench formation simplicityVSAvoiddevice reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements preliminary action by intentionally forming the isolating trench with a negative displacement relative to the active layer surface before the final etching step. This preliminary offset allows the subsequent etching to create the desired positive displacement with rounded edges, improving reliability while keeping the manufacturing process straightforward through a systematic two-stage approach.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of FDSOI transistors by minimizing structural anomalies and achieving the desired thickness, while maintaining a simple and cost-effective production process.

Implementation Method 1

simultaneous etching, preferably dry etching: i) of a portion of the thickness of the active layer of the second active region so as to form at least one tapered active layer

Methodology Applied
Scientific EffectDry etching:

Data Source

PatentUS11011547B2Method for forming a microelectronic device
Publication Date: 2021.05.18 X FAB FRANCE
  • US11011547B2 patent drawing
  • US11011547B2 patent drawing
  • US11011547B2 patent drawing

AI summary

A method for forming an electronic device comprising a first transistor and a second transistor, from a stack of layers comprising an isolating layer surmounted on an active layer made of a semi-conductive material, the method comprising at least the following steps: Forming an isolating trench to define, in the active layer, at least one first active region and at least one second active region, said isolating trench protruding with respect to the active layer of the second active region; Forming a masking layer without covering the active layer of the second active region and without covering a portion of the isolating trench; Etching: of a portion of the thickness of the active layer of the second active region, and of at least one portion of the thickness of said portion of the isolating trench.