FDSOI Threshold Voltage Tuning via Selective Buried Oxide Ion Implantation
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Solution Overview
Problem
The integration of multiple effective work function (WF) gate stacks on a single chip for both low-power (LP) and high-performance (HP) CMOS devices, such as NMOS and PMOS devices, is challenging due to the need for additional processing steps and potential adverse effects on other devices from ion implantations like Fluorine, which modulate the WF.
Innovation Solution
A method involving the formation of masks to selectively expose different semiconductor devices for ion implantation, allowing for the alteration of threshold voltages in semiconductor on insulator (SOI) devices, using a metal gate stack with a suitable effective WF for one type of device and selectively performing ion implantation with dopants like Fluorine to achieve desired threshold voltages for other devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is performed to modulate the effective work function of gate stacks, then the threshold voltage of specific CMOS devices can be adjusted, but other devices on the same chip may be adversely affected
Solution Approach 1:
The chip is divided into different regions with distinct threshold voltage requirements. By performing ion implantation in a segmented manner on different chips and then integrating them through wafer-level or chip-level bonding, the harmful effects of ion implantation are confined to specific regions, preventing adverse effects on other devices with different threshold voltage requirements.
Solution Approach 2:
A buried oxide layer serves as an intermediary that electrically isolates different semiconductor devices on the same chip. This intermediary layer allows adjacent devices to have different threshold voltages without interfering with each other's operation, enabling the integration of both low-power and high-performance devices on a single chip.
2Adaptability or versatility
If multiple gate stacks with different effective work functions are formed individually, then different threshold voltages can be achieved for LP and HP CMOS devices, but additional processing steps are required
Solution Approach 1:
A single gate stack structure with a universal effective work function is designed to serve multiple functions. By combining this universal gate with semiconductor devices having different channel types (NMOS, PMOS) and different operational requirements, multiple threshold voltage configurations are achieved without forming separate gate stacks for each device type, thereby reducing processing complexity.
Solution Approach 2:
Instead of changing the gate stack's effective work function through multiple formation processes, the threshold voltage is adjusted by changing parameters of the semiconductor device itself, such as channel doping concentration and channel thickness. This approach allows multiple threshold voltages to be achieved while maintaining a simple, unified gate stack formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of semiconductor devices with varying threshold voltages on a single chip without adversely affecting other devices, allowing for the integration of multiple performance levels through selective ion implantation and suitable metal gate stack selection.
Implementation Method 1
performing an ion implantation to alter a threshold voltage of the at least one second-type semiconductor device
Data Source
AI summary
Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconductor device to be included on a chip. Then, an ion implantation, with a dopant such as F, can be selectively performed to achieve proper Vt for other semiconductor devices on the chip.