FDSOI Transistor Gate Coupled to Ground Plane
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Solution Overview
Problem
In FDSOI technology, achieving distinct threshold voltages for transistors is challenging due to minimal channel doping variations, making it difficult to produce integrated circuits with both low-power and high-slew rate logic gates, and the manufacturing process is complex and costly.
Innovation Solution
The solution involves increasing the coupling between the gate and channel of FDSOI transistors by covering the side and upper faces of the channel with a gate and arranging part of the gate at a distance from the buried insulation layer, allowing for independent biasing of the ground plane to modulate the threshold voltage, thereby enabling the production of transistors with different threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate covers only the upper face of the channel (conventional planar gate), then the manufacturing process is simple, but the electrostatic control of the channel is insufficient
Solution Approach 1:
The gate structure transitions from a conventional planar configuration covering only the upper face to a multi-dimensional configuration that envelops the channel from multiple directions. The gate covers the upper face and extends laterally to cover side faces of the channel, creating a three-dimensional electrostatic control structure that significantly improves channel control while remaining compatible with standard semiconductor manufacturing processes.
Solution Approach 2:
The gate structure is nested around the channel, with the gate material surrounding the channel region. The gate covers the upper face and extends to envelop the side faces, creating a nested configuration where the gate is positioned around the channel in multiple spatial dimensions, maximizing electrostatic control coverage.
2Manufacturing precision
If the channel width is increased to improve electrostatic control, then the electrostatic control improves, but the short channel effects increase
Solution Approach 1:
Instead of increasing channel width to improve electrostatic control, the invention utilizes vertical and lateral gate coverage to achieve enhanced control. The gate envelops the channel from the upper face and side faces, providing electrostatic control in multiple dimensions without requiring an increased channel width, thereby avoiding the exacerbation of short channel effects.
Solution Approach 2:
The gate structure employs a composite configuration combining conventional upper gate coverage with lateral gate extensions. This composite gate structure achieves superior electrostatic control by integrating multiple coverage geometries, allowing effective channel control without modifying the channel dimensions in a way that would worsen short channel effects.
3Adaptability or versatility
If the doping level of the channel is varied to achieve different threshold voltages, then distinct threshold voltages can be obtained, but the manufacturing process becomes complex and costly
Solution Approach 1:
The invention implements local quality variations through selective ground plane doping rather than channel doping. Different regions of the ground plane can have different doping levels, which locally modulate the threshold voltage of transistors formed above those regions. This approach achieves threshold voltage differentiation while avoiding the complexity of varying channel doping levels.
Solution Approach 2:
The ground plane serves as an intermediary structure between the substrate and the channel, mediating the threshold voltage control. By doping the ground plane rather than the channel, the invention uses the ground plane as an intermediate element to achieve threshold voltage modulation, simplifying the manufacturing process while maintaining the ability to produce transistors with different threshold voltages.
4Manufacturing precision
If the gate is positioned close to the ground plane to increase coupling, then the electrostatic control improves, but the risk of electrical interference increases
Solution Approach 1:
A thin insulating oxide layer is introduced as an intermediary between the gate and the ground plane. This intermediary layer allows the gate to be positioned close to the ground plane for enhanced electrostatic control while preventing direct electrical contact and potential interference. The insulating layer acts as a barrier that maintains strong electrostatic coupling without enabling harmful electrical interactions.
Solution Approach 2:
A thin insulating oxide film is used to separate the gate from the ground plane. This thin film provides electrical isolation while maintaining close proximity for optimal electrostatic control. The flexible nature of the thin film allows the gate to be positioned at an optimized distance from the ground plane without compromising electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrostatic control, reduces short channel effects, and facilitates the production of transistors with reduced threshold voltage dispersions, enabling faster switching and more efficient power management.
Implementation Method 1
increasing the coupling between the gate and channel of an FDSOI transistor by covering on the one hand a side face and an upper face of the channel by this gate, and by arranging on the other hand at least one part of the gate at a distance from a ground plane less than the thickness of a layer of buried insulation separating this ground plane from the channel
Implementation Method 2
By playing on the doping of the ground planes and on their polarization, it is possible to define a range of threshold voltages for the various transistors
Data Source
Figure 1~3
Figure 4~6
Figure 7~8
AI summary
The circuit (1) has a silicon layer placed over a buried insulating layer (130) and separated from a ground plane (140). A fully depleted silicon on insulator (FDSOI) transistor (2) includes a source and a drain arranged on the silicon layer, and a gate (111) covering an upper face of a channel (161). A lateral portion (113) covering a side face of the channel is placed above the ground plane, where a distance between the lateral portion and the ground plane is less than the thickness of the buried insulation layer between the ground plane and the silicon layer. An independent claim is also included for a method for manufacturing an integrated circuit.