FDSOI IC Well Sharing for Threshold Voltage Modulation
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Solution Overview
Problem
Integrated circuits using FDSOI technology face challenges in achieving distinct threshold voltages for transistors due to the lack of channel doping variations, leading to complex designs and long bias diffusion times, which complicates the formation of contacts and increases surface area requirements, affecting integration density and efficiency.
Innovation Solution
The design incorporates a bias circuit generating bias voltages applied to via-type interconnections, with doped ground planes and wells to modulate threshold voltages, allowing for efficient biasing of transistors with opposite doping types, reducing the complexity of contact formation and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If distinct threshold voltages are achieved by differentiating channel doping levels, then threshold voltage modulation is possible, but this approach is impossible in FDSOI technology where channel doping is almost zero
Solution Approach 1:
The patent changes the parameter used for threshold voltage modulation from channel doping level to ground plane doping level and biasing voltage. By adjusting the doping concentration and bias voltage applied to the ground plane, distinct threshold voltages (LVT, HVT, SVT) are achieved without modifying the channel doping, thus maintaining FDSOI advantages while enabling threshold voltage differentiation.
Solution Approach 2:
The ground plane acts as an intermediary element between the substrate and the transistor channel. By doping the ground plane and applying bias voltages to it, the electric field in the channel is modulated, thereby controlling the threshold voltage. This intermediary approach allows threshold voltage modulation without direct channel doping.
2Adaptability or versatility
If multiple ground planes with different doping types are used to achieve distinct threshold voltages, then transistor threshold voltage differentiation is possible, but the bias diffusion time becomes relatively long and contact formation becomes complex
Solution Approach 1:
The patent merges the biasing functions for multiple ground planes into a single shared well structure. The well provides a common biasing path that simultaneously biases multiple ground planes with different doping types, reducing the number of separate biasing circuits and contacts needed. This merging approach shortens the bias diffusion path and simplifies contact formation while maintaining threshold voltage differentiation.
3Adaptability or versatility
If multiple separate contacts are formed to bias different ground planes, then distinct threshold voltages can be achieved, but the surface area required increases, affecting integration density
Solution Approach 1:
The shared well structure serves multiple functions simultaneously: it acts as a biasing path for multiple ground planes, provides electrical connection for multiple transistors, and functions as a substrate extension. This multi-functional design eliminates the need for separate contacts for each ground plane, reducing the total surface area required while maintaining the capability to achieve distinct threshold voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and simplified biasing of transistors with reduced biasing time and surface area requirements, enhancing integration density and operational efficiency while maintaining the advantages of FDSOI technology.
Implementation Method 1
a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component... a first well having a second type of doping opposite that of the first type
Implementation Method 2
long bias diffusion times, which complicates the formation of contacts
Data Source
AI summary
A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.