Ferroelectric Memory Cache Counter Replacement
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Solution Overview
Problem
The complexity of hardware construction in semiconductor storage apparatuses using ferroelectric memory is increased by the need to manage data use states for replacement algorithms like LRU and NRU, which complicates the design and increases power consumption.
Innovation Solution
A semiconductor storage apparatus with a ferroelectric memory and a cache memory system that uses a counter to determine data replacement independently of data use states, simplifying hardware construction and reducing power consumption by allowing data to be written directly to the cache memory upon read or rewrite requests, and optionally switching between power-saving and non-power-saving modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If replacement algorithms like LRU or NRU are used to determine which data block to replace in cache memory, then data replacement efficiency is improved, but hardware construction complexity increases due to the need to manage data use states
Solution Approach 1:
The patent extracts the complex data use state management functionality from the replacement algorithm and replaces it with a simple counter that only needs to track the number of cache misses. This removes the need for complex hardware components that would otherwise be required to track and manage data access patterns, thereby reducing hardware complexity while maintaining replacement functionality.
Solution Approach 2:
The patent changes the parameter being tracked from detailed data use states (access patterns, timestamps, etc.) to a simple numerical parameter (cache miss count). This parameter transformation allows the system to make replacement decisions based on a single counter value rather than complex state information, significantly simplifying the hardware construction.
2Productivity
If replacement algorithms like LRU or NRU are used to manage cache memory, then data replacement efficiency is improved, but power consumption increases due to the need to update management information
Solution Approach 1:
The patent removes the power-consuming data use state management operations and replaces them with a simple counter increment operation. This extraction of unnecessary complexity directly reduces power consumption while maintaining the essential cache replacement functionality.
Solution Approach 2:
The counter automatically increments on cache misses without requiring complex control logic or state management. This self-service mechanism eliminates the need for power-consuming management operations while still providing effective cache replacement based on simple miss count tracking.
3Duration of action of stationary object
If a cache memory is incorporated into a semiconductor storage apparatus to extend ferroelectric memory life, then the life of the semiconductor storage apparatus is extended, but hardware construction complexity increases
Solution Approach 1:
The patent extracts the complex replacement algorithm logic from the cache memory system and replaces it with a simple counter-based approach. This allows the cache memory to be incorporated for extending storage apparatus life while avoiding the hardware complexity that would otherwise be required for sophisticated replacement algorithms.
Solution Approach 2:
The simple counter serves multiple functions: it tracks cache misses, determines replacement candidates, and controls cache write operations. This multi-functionality reduces the need for separate hardware components, thereby extending storage life without proportionally increasing hardware complexity.
Data Source
AI summary
A semiconductor storage apparatus comprising: a ferroelectric memory; an SRAM 30; a counter 41; a CAM 10 that judges whether or not a block of data requested to be read out from the ferroelectric memory is stored in the SRAM 30; a storage control unit 51 that, if a result of the judgment is negative, performs a control to read out the requested block of data from the ferroelectric memory and stores a copy of the read-out block of data into a unit storage area in the SRAM 30 that corresponds to the count value indicated by the counter 41; and a counter control unit 52 that causes the counter 41 to update the count value each time a result of the judgment is negative.