Feature-Model Process Recipes for Wafer Parameter Optimization
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Solution Overview
Problem
Semiconductor wafer processing complexity increases with shrinking device sizes, leading to inefficient process optimization due to numerous process control variables and insufficient in-line precision metrology, resulting in sub-optimal recipes and resource wastage.
Innovation Solution
The use of machine learning feature models to create and match process recipes by determining predicted processing parameters based on target properties, optimizing recipe settings through numerical optimization routines and generating offsets to correct for process disruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional DoE methods are used with limited wafers for process optimization, then manual tuning and expertise are required, but resource consumption increases and optimal results are not achieved
Solution Approach 1:
The patent creates virtual copies of wafers through simulation models that replicate physical wafer behavior. These digital twins allow extensive process optimization experiments to be conducted in silico, eliminating the need to consume physical wafers for DoE while maintaining optimization accuracy. The virtual wafer models include layer structures, material properties, and process responses that mirror real wafers.
Solution Approach 2:
The system performs preliminary process optimization through computational simulations before actual wafer processing. By pre-calculating optimal process parameters using trained machine learning models and running virtual experiments, the system identifies best practices in advance, avoiding the need to consume physical wafers during the optimization phase.
2Manufacturing precision
If comprehensive process parameter tuning is performed to achieve optimal results, then manufacturing precision improves, but processing time and complexity increase
Solution Approach 1:
The system performs comprehensive process optimization calculations in advance through automated simulations and stores the results in lookup tables. When a real wafer needs processing, the pre-computed optimal parameters are quickly retrieved and applied, achieving high manufacturing precision without the time penalty of real-time optimization.
Solution Approach 2:
The patent divides the complex optimization problem into manageable segments by creating separate virtual wafer models for different process stages and parameter ranges. This segmentation allows parallel processing of multiple optimization scenarios, reducing the overall computational time while maintaining comprehensive coverage of the parameter space.
3Measurement precision
If traditional metrology methods are used for process verification, then measurement precision is achieved, but processing speed decreases due to destructive techniques
Solution Approach 1:
The patent uses virtual wafer models as digital copies that can be measured and analyzed without consuming the physical wafer. These virtual models contain all the process information and can be queried infinitely fast for verification, providing measurement precision equivalent to physical metrology without the time cost or destructive nature of techniques like TEM.
Solution Approach 2:
The system performs self-verification by comparing simulated process outcomes against target specifications using the virtual wafer models. This self-service approach eliminates the need for external destructive metrology measurements, as the simulation inherently provides predicted outcomes that can be immediately verified against requirements.
4Reliability
If extensive DoE experiments are conducted to optimize process parameters, then process capability improves, but the number of required wafers and resources increases significantly
Solution Approach 1:
The patent replaces physical wafers with virtual wafer models that can be used indefinitely for experimentation. These digital copies allow extensive DoE with multiple parameter variations, repetitions, and edge cases without consuming any additional physical wafers, thus improving process capability while maintaining wafer quantity at minimal levels.
Solution Approach 2:
The system explores the parameter space efficiently by using machine learning models to predict outcomes and guide the search for optimal parameters. Instead of exhaustively testing all parameter combinations on physical wafers, the system intelligently navigates the parameter space using virtual simulations, achieving high process capability with far fewer physical resources.
Data Source
AI summary
A method includes determining, by a processing device, whether a first process recipe including a set of Pareto efficient parameters is to be selected from a set of process recipes, wherein the set of Pareto efficient parameters fail to satisfy each target property of a set of target properties for processing the component, in response to determining that a first process recipe is not to be selected from a set of process recipes for processing the component, selecting, by the processing device from the set of process recipes, a second process recipe including a set of parameters satisfying each target property of the set of target properties, and causing, by the processing device, the component to be processed by a process tool using the second process recipe.