Convolution Feature Plane Grouping to Cut Register Setup Time
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Solution Overview
Problem
Existing neural network processing methods face inefficiencies due to excessive memory usage and reduced operation speed when handling complex networks with varying feature plane sizes and kernel sizes, as they either require excessive memory for maximum sizes or prolonged register setup times.
Innovation Solution
A processing apparatus that hierarchically groups feature planes based on common operation processing, using a controller to manage a common control parameter memory for each group, optimizing register settings and reducing unnecessary operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the register is set for each processing node (convolution operation) to handle various feature plane sizes and kernel sizes, then the processing can be performed with maximum adaptability, but the register setup time increases and operation speed decreases
Solution Approach 1:
The patent segments feature planes into groups based on their operational characteristics. Instead of configuring registers individually for each feature plane, multiple feature planes with similar processing requirements are grouped together and share common register settings. This segmentation approach maintains adaptability to handle various sizes while reducing the frequency of register reconfiguration, thereby resolving the contradiction between adaptability and setup time.
Solution Approach 2:
The patent implements universality by creating groups of feature planes that can share the same register configuration. A single set of registers can serve multiple feature planes within a group, allowing the system to handle diverse feature plane sizes and kernel sizes without requiring dedicated registers for each. This multi-functional approach reduces register setup time while maintaining the ability to process various configurations.
2Ease of operation
If the register is set for each layer to control convolution operation processing, then the control is comprehensive, but the device complexity increases
Solution Approach 1:
The patent merges the control of multiple feature planes into unified groups that share common register settings. Instead of maintaining separate register configurations for each feature plane or layer, the system combines control parameters for groups of feature planes, reducing the overall number of registers and configuration complexity while preserving comprehensive control capability through group-level management.
Solution Approach 2:
The patent applies universality by designing register structures that can serve multiple feature planes simultaneously. A single register configuration can control convolution operations across multiple feature planes within a group, reducing device complexity while maintaining ease of operation through standardized group-based control mechanisms.
3Adaptability or versatility
If memory is allocated for maximum feature plane sizes to handle all processing cases, then the processing coverage is complete, but memory usage becomes excessive
Solution Approach 1:
The patent segments feature planes into groups based on their size and processing requirements. Memory allocation is optimized for each group rather than allocating maximum memory for all cases. This segmentation allows the system to process various feature plane sizes by activating only the necessary memory regions for each group, maintaining complete processing coverage while significantly reducing overall memory usage.
Solution Approach 2:
The patent applies local quality by allocating memory resources according to the specific requirements of each feature plane group. Instead of uniformly allocating maximum memory throughout the system, memory is allocated locally and specifically for each group's needs. This approach ensures that each group has sufficient memory for its processing requirements while avoiding excessive memory allocation system-wide, thus resolving the contradiction between processing coverage and memory usage.
Data Source
AI summary
A processing apparatus has feature plane storage that stores feature plane data. The apparatus has a coefficient storage that stores weight coefficient data. The apparatus has a calculation circuit that performs convolution operation processing using the stored weight coefficient on feature plane data of a feature plane that is supplied by the feature plane storage to the calculation circuit. The apparatus has a parameter storage configured to store a common control parameter for each feature plane group. A plurality of feature planes are grouped into the feature plane group based on commonality of operation processing such that a feature plane to be referred to in the operation processing for calculating the feature plane data of each of the plurality of feature planes is common.