Lithography Feature Rotation for Uniform Josephson Junction Fabrication
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Solution Overview
Problem
Existing fabrication processes for quantum computing circuit elements, such as Josephson junctions, result in non-uniform critical dimensions across a substrate due to variations in deposition angles, source-to-substrate distances, and shadowing effects, leading to inconsistent performance and resistance variations among circuit elements.
Innovation Solution
A modified lithography mask write file is generated by applying a rotation function to align feature orientations with process vectors, compensating for non-uniformities in deposition processes, ensuring consistent critical dimensions and improved uniformity across the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography mask write files are used without rotation compensation, then the fabrication process is simple and quick, but the critical dimensions of circuit elements become non-uniform across the substrate due to deposition angle variations
Solution Approach 1:
The patent applies preliminary action by pre-calculating and applying rotation values to features in the lithography mask write file before fabrication. The system determines the orientation of each feature relative to process vectors (deposition flux vectors) and rotates features to align with these vectors, compensating for deposition non-uniformities before the actual fabrication process begins. This advance preparation eliminates the need for complex real-time adjustments during manufacturing.
Solution Approach 2:
The patent implements local quality by applying different rotation values to different features based on their specific locations and orientations on the substrate. Instead of using a uniform approach, the system calculates individual rotation values for each feature by determining the angle between the feature's orientation vector and the process vector at that location. This localized compensation ensures optimal critical dimension uniformity for each feature according to its specific geometric relationship with the deposition source.
2Manufacturing precision
If features are rotated to align with process vectors, then deposition uniformity improves, but the lithography mask write file generation becomes more complex and computationally intensive
Solution Approach 1:
The patent replaces complex mechanical or manual alignment processes with computational methods. The system uses automated calculations to determine rotation values by computing angles between feature vectors and process vectors, then applies these rotations programmatically to the lithography mask write file. This substitution of computational algorithms for manual or mechanical alignment procedures simplifies the overall process despite the mathematical computations involved.
Solution Approach 2:
The system implements self-service by automatically determining feature orientations, calculating appropriate rotation values, and applying corrections to the lithography mask write file without requiring external intervention. The fabrication system uses its own process vector information and feature geometry data to autonomously generate the compensated mask file, eliminating the need for separate measurement and adjustment steps.
3Productivity
If larger wafer sizes are used to increase productivity, then more circuit elements can be fabricated simultaneously, but non-uniformities in deposition angles and source-to-substrate distances increase across the wafer surface
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the orientation parameters (rotation values) of features based on their location on the wafer. The system calculates rotation values that account for variations in source-to-substrate distance and deposition angles across different regions of the wafer. This allows larger wafers to be processed while maintaining uniform critical dimensions by adapting feature orientations to local geometric conditions.
Solution Approach 2:
The patent segments the wafer surface into multiple regions, each with its own characteristic process vectors and geometric relationships. Instead of treating the entire wafer as a uniform surface, the system determines individual rotation values for features in different locations, effectively segmenting the compensation strategy to match the spatial variation in deposition conditions across the large wafer surface.
Data Source
AI summary
A method for fabricating a circuit element on a substrate by a fabrication system including obtaining a write file including information characterizing features arranged at multiple locations with respect to a surface of the substrate, each feature having a first end and a second end defined along a first feature direction of the feature, generating, for each of the multiple locations and using a geometric relationship defined between a process vector of a process source of the fabrication system and the location of the feature on the substrate, a rotational value, and modifying the write file to generate a modified write file including for at least one feature of the multiple features at a respective location with respect to the surface of the substrate, rotating the first feature direction of the feature about an axis normal to the surface of the substrate by the rotation value.