Featured Scan Pattern Generation for SoC Defect Detection
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Solution Overview
Problem
The increasing complexity of nanometer scaling in system-on-chip (SoC) products makes it difficult to achieve high fault coverage in digital circuitry, leading to defects that are not caught during traditional scan testing, resulting in defective parts per million (DPPM) and the need for additional system-level testing, which is costly and time-consuming.
Innovation Solution
Performing scan testing under non-destructive stress conditions, including voltage and temperature extremes, and above maximum operating frequency, to expose hidden defects and collect test responses, which are then analyzed using outlier analysis and machine learning to generate featured test patterns that predict downstream failures, thereby reducing reliance on system-level testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan testing is performed under normal conditions, then test cost and time are controlled, but defect detection capability is insufficient leading to high DPPM
Solution Approach 1:
The patent applies preliminary action by performing stress condition scan testing during the production test flow before chips are shipped to customers. This early detection under stress conditions (temperature extremes, voltage variations, frequency scaling) identifies potential defects that would not be caught under normal operating conditions, preventing defective chips from reaching the customer and reducing DPPM.
Solution Approach 2:
The patent utilizes parameter changes by varying operating conditions during testing - specifically changing temperature, voltage, and frequency parameters to create stress conditions. This allows the test to expose timing-related defects and other issues that only manifest under extreme conditions, thereby improving defect detection capability without requiring additional physical test equipment.
2Reliability
If system-level testing is added to catch functional defects, then product quality improves, but test cost and throughput are negatively impacted
Solution Approach 1:
The patent introduces an intermediary approach by using stress condition scan testing as a middle ground between traditional scan testing and full system-level functional testing. This intermediate test method uses modified scan patterns applied under stress conditions to detect functional defects that would otherwise require complete SLT, thereby improving product quality while maintaining higher throughput compared to full SLT.
Solution Approach 2:
The patent extracts the essential defect-detection functionality from comprehensive system-level testing and isolates it into a streamlined stress condition scan test. By extracting only the critical detection capabilities needed to catch timing defects and functional issues under stress, the patent achieves improved product quality without the full cost and throughput penalty of complete SLT.
3Reliability
If scan pattern count is increased to achieve high fault coverage, then defect detection improves, but test cost increases
Solution Approach 1:
The patent applies dynamics by adapting the scan testing approach to different operating conditions dynamically. Instead of using a fixed large set of scan patterns at normal conditions, the patent uses frequency scaling and voltage modulation to dynamically change the test environment, allowing fewer patterns to achieve equivalent or superior fault coverage by targeting specific defect types that manifest under stress conditions.
Data Source
AI summary
An method of generating a featured scan pattern for test includes: providing a plurality of predetermined test patterns to perform test on a plurality of devices under test (DUT) under a stress condition to generate a plurality of test responses of each DUT; grouping a plurality of specific test responses of each DUT from the test responses of each DUT to determine a feature value corresponding to a failure feature for each DUT; and generating at least one featured test pattern according to the feature value of each DUT.