Conditional FEC Hardware Acceleration for Decrypt-Decode Ordering
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Solution Overview
Problem
Traditional FEC processing in software slows down data packet processing, while hardware acceleration is hindered by the changing nature of FEC standards, necessitating a robust technique for conditional hardware acceleration to enhance network performance.
Innovation Solution
The system determines whether to hardware decrypt data packets before or after decoding based on available FEC conditions and hardware acceleration availability, optimizing the order of processing for improved network performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FEC processing is performed in software, then flexibility for implementing new protocols is improved, but processing speed deteriorates
Solution Approach 1:
The system segments FEC processing into two distinct parts: a hardware acceleration engine that handles computationally intensive operations at high speed, and a software component that manages protocol flexibility and control logic. This segmentation allows each component to optimize for its specific function, resolving the contradiction between speed and flexibility.
Solution Approach 2:
The patent introduces an intermediary layer that coordinates between software FEC implementations and hardware acceleration capabilities. This intermediary manages the division of labor, routing appropriate processing tasks to either software or hardware based on current needs, thereby maintaining both flexibility and high processing speed.
2Speed
If hardware acceleration is used for FEC processing, then processing speed is improved, but adaptability to changing FEC standards deteriorates
Solution Approach 1:
The hardware acceleration engine is designed with dynamic reconfigurability, allowing it to adapt its processing capabilities based on the specific FEC standard being used. This dynamic architecture enables the hardware to maintain high processing speeds while accommodating changes in FEC standards through runtime configuration rather than fixed design.
Solution Approach 2:
The system utilizes parameter changes to bridge software flexibility with hardware speed. By allowing processing parameters to be dynamically adjusted based on the FEC standard requirements, the hardware can operate at full speed while adapting to different coding schemes, block sizes, and correction levels through parameter modification rather than structural redesign.
3Productivity
If decryption is performed before decoding in hardware, then network throughput is improved, but processing complexity increases
Solution Approach 1:
The system performs decryption as a preliminary action before FEC decoding in the hardware pipeline. By removing encryption earlier in the processing chain, the subsequent decoding operations can proceed more efficiently, improving overall throughput. The hardware architecture is specifically designed to handle this preliminary decryption step without significantly increasing complexity.
Data Source
AI summary
It is determined whether hardware acceleration is available for the incoming data packet. Responsive to hardware acceleration availability, and based on the received FEC conditions, it is determined, for a session associated with the incoming data packet, whether to hardware decrypt the incoming data packet before decoding the incoming data packet or to hardware decrypt after decoding the incoming data packet.