FEC Parameter Adaptation Using Post-FEC BER Feedback

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Solution Overview

Problem

Conventional communication systems lack the ability to optimize post-FEC bit error rate (BER) performance due to static FEC and link parameters, which are typically adjusted based on pre-FEC criteria, failing to account for post-FEC performance metrics.

Innovation Solution

Adaptation metrics reflective of post-FEC BER performance are introduced to dynamically adjust FEC-related and link parameters, using codeword histogram difference and FEC symbol error auto-correlation functions to optimize post-FEC BER performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If static FEC and link parameters are used, then device complexity is reduced, but post-FEC BER performance deteriorates

Engineering Contradiction:
Improveparameter adjustment mechanismVSAvoidpost-FEC BER performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements dynamic parameter adjustment by introducing adaptation metrics that continuously monitor post-FEC BER performance and automatically adjust FEC and link parameters in real-time, transforming the static parameter system into a dynamic one that adapts to changing channel conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent establishes a feedback loop where post-FEC BER performance metrics are measured and fed back to the parameter adjustment mechanism, enabling the system to learn from performance outcomes and optimize parameters iteratively, thereby improving reliability without excessive complexity

Inventive Principle:
Principle #23Feedback

2Reliability

If dynamic parameter adjustment is implemented, then post-FEC BER performance is improved, but device complexity increases

Engineering Contradiction:
Improvepost-FEC BER performanceVSAvoidparameter adjustment mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent focuses on adjusting specific key parameters (FEC parameters and link parameters) rather than redesigning the entire system, using targeted parameter changes to improve performance while limiting the increase in overall device complexity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The adaptation mechanism operates autonomously using self-generated performance metrics to guide parameter adjustments, reducing the need for external control and minimizing the complexity overhead of the dynamic adjustment system

Inventive Principle:
Principle #25Self-service

3Reliability

If adaptation metrics are calculated and parameters are adjusted, then post-FEC BER performance is improved, but latency increases

Engineering Contradiction:
Improvepost-FEC BER performanceVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements periodic parameter adjustment rather than continuous adjustment, updating parameters at optimized intervals based on performance degradation thresholds, thereby reducing the frequency of adjustments and minimizing latency impact while maintaining performance improvements

Inventive Principle:
Principle #19Periodic action

4Reliability

If adaptation metrics are calculated and parameters are adjusted, then post-FEC BER performance is improved, but power consumption increases

Engineering Contradiction:
Improvepost-FEC BER performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial adjustment by modifying only the necessary FEC and link parameters rather than reconfiguring the entire system, using the minimum required adaptation effort to achieve performance improvement while reducing excessive power consumption

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12580814B2Adapting forward error correction (FEC) or link parameters for improved post-FEC performance
Publication Date: 2026.03.17 NVIDIA CORP
  • US12580814B2 patent drawing
  • US12580814B2 patent drawing
  • US12580814B2 patent drawing

AI summary

Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from at least the receiver circuit or the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.