As-Needed FEC Bypass Pipeline for Low-Latency Errorless Traffic
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Solution Overview
Problem
Current forward error correction (FEC) systems in high-performance computing incur significant latency due to routing all traffic through FEC correction blocks, even for errorless data, which contradicts the low-latency goals of HPC environments.
Innovation Solution
Implementing as-needed forward error correction by selectively routing errorless traffic through a bypass pipeline instead of a higher-latency FEC pipeline, using FEC decoders and encoders in switches and host fabric adapters to identify and bypass errorless codewords, and strategically inserting 'bubble codewords' to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all traffic is routed through FEC correction block, then error correction is ensured, but latency increases significantly
Solution Approach 1:
The patent segments the traffic flow into two separate paths: a bypass pipeline for errorless traffic and an FEC correction pipeline for erroneous traffic. The receiver divides incoming codewords into two streams, one routed through the bypass pipeline and another through the FEC correction pipeline, allowing errorless packets to skip correction processing entirely while maintaining error correction capability for problematic packets.
Solution Approach 2:
The system dynamically switches between bypass and FEC correction paths based on real-time error detection. When errors are detected in the bypass pipeline, the system automatically redirects subsequent traffic to the FEC correction pipeline. This dynamic adaptation allows the system to optimize latency when possible while ensuring reliability when needed.
2Reliability
If FEC correction is applied to all data, then errorless data is protected, but processing time increases for all packets
Solution Approach 1:
The patent extracts the FEC correction operation from the universal processing path and applies it selectively only to packets that require it. By using a codeword error detector to identify which packets have errors, the system removes unnecessary correction processing from errorless packets, thereby improving overall processing speed while maintaining protection for erroneous packets.
Solution Approach 2:
Different quality levels of processing are applied to different packets based on their error status. Errorless packets receive minimal processing through the bypass pipeline, while erroneous packets receive full FEC correction processing. This local differentiation of processing quality optimizes the balance between reliability and productivity across the entire data stream.
3Loss of time
If bypass pipeline is used for errorless traffic, then latency is reduced, but system complexity increases
Solution Approach 1:
The patent merges the bypass pipeline and FEC correction pipeline into a unified processing architecture where both pipelines operate in parallel and can be dynamically selected. By combining these two processing paths under a single management structure with unified error detection and routing logic, the system reduces the complexity that would arise from completely separate systems while still achieving the latency benefits of the bypass path.
Data Source
AI summary
An as-needed forward error correction decoder is provided. Embodiments include a forward error correction pipeline (204), a bypass pipeline (202); and bypass selection logic (208) configured to selectively transmit errorless codewords from the bypass pipeline.