Physical-Layer Retransmission Control Using FEC and CRC

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Solution Overview

Problem

High-speed networking systems face challenges with burst errors, which can lead to increased retransmissions and decreased system throughput, resulting in congestion, longer delays, and decreased reliability.

Innovation Solution

The implementation of a hybrid automatic repeat query (H-ARQ) system that combines high-rate forward error correction (FEC) with automatic repeat request (ARQ) error-control, using cyclic redundancy check (CRC) and Reed-Solomon (RS) code correction & detection capabilities to establish double layer protection and improve link integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FEC codes are used to correct burst errors, then error correction capability is improved, but false packet acceptance rate increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidfalse packet acceptance rate
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent combines FEC error correction capability with CRC error detection capability into a unified error control mechanism. The CRC check is performed on the decoded output from the FEC decoder, creating a dual-layer protection system that prevents false packet acceptance while maintaining error correction benefits

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces CRC as an intermediary verification layer between FEC decoding and packet acceptance. The CRC check acts as a mediator that validates whether FEC-corrected packets are truly error-free before accepting them, preventing false positives

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If CRC is applied at the link layer after packet construction, then error detection capability is improved, but transmission latency increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidtransmission latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs CRC calculation and verification at the physical layer before packet construction and link layer processing. By executing the error detection check earlier in the transmission pipeline, the system avoids additional latency that would occur if CRC verification were delayed until the link layer

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent separates CRC verification from the main packet processing flow by implementing it as an independent check at the physical layer. This segmentation allows CRC validation to occur in parallel with packet construction activities, reducing overall transmission latency

Inventive Principle:
Principle #1Segmentation

3Reliability

If dual-layer error protection (FEC + CRC) is implemented, then link integrity is improved, but system complexity increases

Engineering Contradiction:
Improvelink integrityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a unified error control block that handles both FEC decoding and CRC verification functions. By consolidating these error protection mechanisms into a single multi-functional module, the system achieves dual-layer protection without proportionally increasing overall system complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12244416B2Systems and methods of initiating retransmission requests
Publication Date: 2025.03.04 MELLANOX TECHNOLOGIES LTD(IL)
  • US12244416B2 patent drawing
  • US12244416B2 patent drawing
  • US12244416B2 patent drawing

AI summary

A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.