Multi-Stage FEC Decoder Error Mask Compression for Low-Latency Tracking
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Solution Overview
Problem
Existing FEC decoding processes face high latency and inaccurate error statistics due to the iterative nature of turbo-coding schemes, which complicates the evaluation and adjustment of transmission channel characteristics, and requires large memory buffers to store uncorrected data for accurate error masking.
Innovation Solution
A multi-stage decoder circuit with compression and decompression circuits to generate and buffer compressed error masks, reducing memory requirements by compressing error mask data from each decoder stage and decompressing it for combination into a single error mask indicating errors throughout the decoding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If error masks are buffered in uncompressed form to ensure accurate error statistics, then measurement precision is improved, but device complexity and memory requirements increase
Solution Approach 1:
The patent extracts only the essential error information from the error mask and stores it in a compressed format. Instead of buffering complete error masks, the system identifies and stores only the locations and characteristics of errors, significantly reducing memory requirements while preserving the accuracy needed for error statistics calculation.
Solution Approach 2:
The patent changes the representation parameters of error mask data by transitioning from storing complete bit-pattern error masks to storing compressed error information such as error locations, error counts, and error patterns. This parameter transformation reduces the data volume requiring buffering while maintaining the precision necessary for accurate error statistics.
2Productivity
If decoding is performed using multiple pipeline stages to increase throughput, then productivity is improved, but latency increases making error tracking difficult
Solution Approach 1:
The patent segments the decoding process into multiple pipeline stages while implementing error tracking at each stage. Each stage generates its own error mask that is compressed and buffered, allowing the system to maintain high throughput through parallel processing while tracking errors incrementally at each segment rather than waiting for complete decoding.
Solution Approach 2:
The patent performs preliminary error masking and compression at each decoding stage rather than waiting for the final stage. By generating and compressing error masks incrementally as data progresses through the pipeline, the system enables early error statistics calculation and reduces the effective latency for error detection while maintaining high throughput.
3Measurement precision
If complete error masks are buffered until final decode stage to ensure accurate error statistics, then measurement precision is improved, but loss of time increases due to waiting for complete decoding
Solution Approach 1:
The patent performs preliminary error mask generation and compression at intermediate decoding stages rather than waiting for final decoding completion. This allows error statistics to be calculated and made available earlier in the process, reducing the time delay while maintaining accuracy through incremental error tracking and compression.
Solution Approach 2:
The patent introduces a compression circuit as an intermediary between the decoding stages and the error statistics calculation unit. This compression circuit processes error masks incrementally as they become available from each decoding stage, enabling continuous error statistics updates without requiring complete decoding to finish first, thus reducing time loss while maintaining precision.
Data Source
AI summary
In one embodiment, a multi-stage decoder circuit is provided. Each stage of the decoder circuit is configured to perform one or more decoding iterations and produce an error mask indicating errors detected in the decoding stage. A compression circuit is coupled to one or more of the decoder stages and is configured to generate, for each of one or more of the plurality of decoder stages, a respective compressed error mask from the error mask produced by the decoder stage. A buffer circuit is coupled to the compression circuit and is configured to buffer the compressed error masks. A decompression circuit is coupled to the buffer circuit and is configured to decompress each of the compressed error masks. A combination circuit is coupled to the decompression circuit and is configured to combine the decompressed error masks into a single error mask.