FEC Decoder State Recompute for Late Packet Erasures

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Solution Overview

Problem

Existing forward error correcting (FEC) schemes in packet networks suffer from bit errors and increased bit error rates due to the discarding of late packets, which are not effectively addressed by conventional decoding methods.

Innovation Solution

A method and system that utilize the information from late packet arrivals to update and recompute the state of the decoder, effectively mitigating the impact of late packet erasures by using a late packet arrival processing unit to update an auxiliary buffer and decoder state, thereby improving the bit error rate performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If late packets are discarded to maintain real-time signal quality, then packet delay is reduced, but bit error rate increases due to loss of redundant information

Engineering Contradiction:
Improvepacket delayVSAvoidbit error rate
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent stores redundant information from late packets in a buffer before final decoding, allowing the decoder to access this information when needed for error correction, thus preparing the data in advance for potential use

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary buffer that holds late packet data between reception and decoding, allowing the system to utilize late-arriving redundant information without causing packet delay in the main signal flow

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If FEC redundancy is increased to correct more errors, then reliability improves, but device complexity increases due to larger buffer and processing requirements

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoder complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent processes only the necessary portion of late packet data that is relevant to current decoding needs, rather than processing all redundant data, thus achieving adequate error correction without excessive complexity

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent applies error correction selectively to specific packets or data segments that benefit from FEC, rather than uniformly processing all data, optimizing the balance between reliability and complexity

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7447983B2Systems and methods for decoding forward error correcting codes
Publication Date: 2008.11.04 VERIZON PATENT & LICENSING INC
  • US7447983B2 patent drawing
  • US7447983B2 patent drawing
  • US7447983B2 patent drawing

AI summary

Systems and methods for improving the performance of decoders of forward error correcting codes use the information contained in late packet arrivals to update (or recompute) the state of the decoder. These systems and methods are generally applicable to decoders that maintain state information in decoding successive bits or information frames so as to improve the performance (i.e., the bit error rate) of the decoder since the recomputed state is exactly the state that the decoder would have had if the information contained in the late packet had originally arrived on time and been decoded in a usual manner. In effect, the updating of the decoder state following a late packet arrival terminates the propagation in time of the effect of the late packet erasure on the state of the decoder.