FEC Decoder Logic Gate Power Optimization
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Solution Overview
Problem
Communication systems using forward error correction (FEC) encoders and decoders, which contain multiple logic gates, face inefficiencies in power consumption due to toggling activity affecting a large number of logic gates, leading to increased power usage and physical size.
Innovation Solution
An analysis application identifies logic gates affected by toggling activity and replaces them with fewer, non-affected logic gates, resulting in a new logic gate design that consumes less power and maintains functionality, reducing the number of logic gates, clock buffers, and wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic gates are designed to handle toggling activity in FEC decoding, then functionality and reliability are improved, but power consumption and device size increase
Solution Approach 1:
The patent changes the operational parameters of logic gates by identifying and eliminating toggling activity that does not contribute to useful computation. By analyzing the toggling patterns and removing redundant transitions, the design maintains necessary functionality while reducing unnecessary power consumption associated with gate switching activity.
Solution Approach 2:
The patent applies local optimization to specific logic gates within the FEC decoder by identifying which individual gates experience harmful toggling activity. Rather than redesigning the entire system, the approach targets specific local regions (individual gates or gate combinations) where toggling can be eliminated through reconfiguration or removal, thereby reducing power consumption locally while preserving overall system reliability.
2Reliability
If logic gates are designed to handle toggling activity, then functionality is maintained, but physical size and capacitance increase
Solution Approach 1:
The patent modifies the design parameters of the logic gate network by changing which gates are present and how they are configured. By eliminating gates that only handle redundant toggling activity, the physical area and capacitance are reduced while the essential decoding functionality is preserved through reconfigured logic paths.
Solution Approach 2:
The patent extracts and removes unnecessary logic gates from the FEC decoder design that contribute to increased physical size and capacitance without providing essential functionality. By taking out these redundant gates and their associated wiring, the design achieves smaller physical footprint and lower capacitance while maintaining decoding accuracy.
3Reliability
If traditional logic gate design is used, then complete functionality is achieved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent changes the design parameters by optimizing the logic gate configuration to eliminate redundant components. By analyzing the toggling activity patterns and reconfiguring the logic network, the design achieves the same error correction capability with fewer gates and simpler interconnections, thereby reducing manufacturing complexity and cost.
Solution Approach 2:
The patent merges or consolidates logic functions by eliminating separate gates that handle redundant toggling activity. By combining necessary logic operations into more efficient gate configurations and removing unnecessary intermediate gates, the design reduces overall complexity while maintaining complete error correction functionality.
Data Source
AI summary
A computing device is configured to analyze a logic gate design having logic gates. The computing device is configured further to identify logic gates that are affected by toggling activity associated with an input of one or more of the logic gates. The computing device is configured further to replace, within the logic gate design, the identified logic gates with different logic gates that are not affected by the toggling activity; and output a new logic gate design based on replacing the identified logic gates with the different logic gates, the application specific integrated circuit, with the new logic gate design, producing a same output as the application specific integrated circuit with the logic gate design, based on same inputs.