Forward Error Correction Decoder Parallel Initialization

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Solution Overview

Problem

Conventional forward error correction (FEC) decoders experience significant latency during initialization due to handshaking delays between the lock state machine and framer, affecting frame alignment and error correction efficiency.

Innovation Solution

The proposed solution involves a decoder configuration where the framer and lock state machine perform parallel evaluations and slips during initialization, allowing continuous frame alignment testing and eliminating latency, with a 32-bit syndrome check and 1-bit slip mechanism, enabling efficient error correction and output formatting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional handshaking protocol is used between lock state machine and framer, then frame alignment accuracy is maintained, but initialization latency increases significantly

Engineering Contradiction:
Improveframe alignment accuracyVSAvoidinitialization latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The framer performs syndrome checks and slips in parallel with the lock state machine evaluating results, preparing frame alignment decisions beforehand rather than waiting for sequential handshaking completion. This preliminary parallel processing eliminates initialization latency while maintaining alignment accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system maintains continuous frame alignment testing by repeatedly performing syndrome checks and slips without interruption during initialization. The parallel evaluation ensures that useful actions (frame alignment testing) continue without停顿, eliminating the latency caused by conventional handshaking delays.

Inventive Principle:
Principle #20Continuity of useful action

2Loss of time

If parallel syndrome check and slip evaluation is implemented, then initialization latency is reduced, but processing complexity increases

Engineering Contradiction:
Improveinitialization latencyVSAvoidprocessing complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The framer and lock state machine are merged into a coordinated parallel processing system where syndrome checks and slip evaluations occur simultaneously. This integration reduces initialization latency by eliminating handshaking delays while managing complexity through unified control logic.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If two frames of input data are required for initialization, then frame alignment accuracy is ensured, but processing throughput is reduced

Engineering Contradiction:
Improveframe alignment accuracyVSAvoidprocessing throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The parallel syndrome check and slip evaluation perform frame alignment testing preliminarily and continuously on incoming data streams. This eliminates the requirement to buffer two complete frames before initialization, allowing immediate processing and improving throughput while maintaining alignment accuracy through continuous parallel evaluation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8902925B2Forward error correction decoder
Publication Date: 2014.12.02 TEXAS INSTRUMENTS INC
  • US8902925B2 patent drawing
  • US8902925B2 patent drawing
  • US8902925B2 patent drawing

AI summary

A method for determining an initial alignment for a frame of input data is provided. A frame for the input data is set, and the frame is synchronized. Specifically, a syndrome check of the frame is performed using a first predetermined number of bits, and a slip of a second predetermined number of bits is requested following the syndrome check. Evaluation of the syndrome check to determine whether the frame is aligned can then be performed in parallel with the slipping. The evaluation and slipping can then be repeated if the frame is misaligned. When the frame is aligned, a lock condition can be indicated, and the slip performed in parallel with the evaluation indicating that the frame is aligned can be deasserted. In addition, when the frame is aligned, error correction on the frame can be performed, and the error corrected frame can be formatted.