Iterative FEC Decoding for Row-Column Deadlock Recovery
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Solution Overview
Problem
In forward error correction (FEC) decoding, certain error patterns, known as deadlocks, can prevent symbols from being corrected using traditional row or column decoding methods, leading to incomplete error correction in communication systems.
Innovation Solution
A method and circuit for FEC decoding that iteratively alternate between decoding rows and columns, and include a deadlock recovery mechanism to invert bits at intersection points of error-prone rows and columns, allowing for additional decoding iterations to correct errors in deadlock scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional row or column decoding methods are used, then the decoding process is simple, but certain error patterns (deadlocks) prevent symbols from being corrected
Solution Approach 1:
The patent implements dynamic decoding by alternating between row and column decoding operations in multiple iterations. The decoder adapts its operation mode based on the current state of error correction, switching between row-major and column-major processing to overcome deadlock patterns that static single-direction decoding cannot resolve.
Solution Approach 2:
The patent transitions from one-dimensional decoding (processing only rows or only columns) to two-dimensional iterative decoding that alternates between row and column dimensions. This dimensional switching allows the system to approach error patterns from different perspectives, enabling correction of deadlock cases where errors are distributed across both row and column intersections.
2Reliability
If multiple decoding iterations are performed, then more errors can be corrected, but the decoding time increases
Solution Approach 1:
The patent employs periodic alternating decoding where row and column decoding operations are performed in repeating cycles. This periodic switching between decoding directions allows the system to make progress on different types of error patterns in each cycle, achieving better overall correction capability while maintaining a predictable and bounded time structure through controlled iteration limits.
Data Source
AI summary
Methods and circuits are disclosed for forward-error-correction (FEC) decoding. A plurality of symbols are received in an interleaved format of rows and columns of the symbols. A plurality of FEC decoding iterations are performed on the plurality of symbols. Each decoding iteration performs FEC decoding of the rows of the plurality of symbols and performs FEC decoding of the columns of the plurality of symbols. After performing the decoding iterations, rows in error and columns in error of the plurality of symbols are determined. In response to the determined rows in error and the determined columns in error matching a deadlock pattern, symbols at intersections of the determined rows and columns in error are determined. Bits of one or more symbols of the determined symbols are inverted. After the inverting of the bits, one or more of the FEC decoding iterations are performed.