FEC Encoder Memory Layout for Low-Power Optical Links
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Solution Overview
Problem
High-speed optical communication systems face challenges in achieving low power consumption while maintaining strong forward error correction performance, especially at high data rates where bit error rates become unacceptable, and existing error correction codes struggle to approach the Shannon Limit effectively.
Innovation Solution
A forward error correction encoder with a memory structure that employs generalized product codes and iterative decoding, reducing memory access and power consumption by randomly selecting columns and rows for encoding, and using a convolutional format to achieve improved threshold performance close to the Shannon Limit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stronger forward error correction is used to reduce bit error rate at high data rates, then reliability is improved, but power consumption increases
Solution Approach 1:
The memory is segmented into multiple blocks that can be independently accessed. The encoder circuit selectively accesses only the necessary blocks containing input data bits and previously encoded data, rather than accessing the entire memory, thereby reducing power consumption while maintaining error correction performance.
Solution Approach 2:
The encoder performs partial encoding by selecting specific blocks and columns of data rather than processing all data uniformly. This selective approach reduces the computational burden and power consumption while achieving the required error correction through iterative decoding of selected portions.
2Reliability
If memory access is increased to improve error correction performance, then reliability is improved, but power consumption increases
Solution Approach 1:
The memory is divided into multiple blocks that can be independently accessed. The encoder selectively accesses only the necessary blocks containing input data bits and previously encoded data, rather than accessing the entire memory, thereby reducing power consumption while maintaining error correction performance.
Solution Approach 2:
Different blocks of memory have different access patterns based on their content. The encoder adapts its access pattern to selectively read from blocks containing relevant data, optimizing the balance between error correction performance and power consumption by accessing only necessary memory locations.
Data Source
AI summary
Consistent with a further aspect of the present disclosure, previously encoded data is stored in a memory, and an encoder accesses both input data and previously encoded data to generate new encoded data or a new codeword. Each codeword is stored in a row of the memory, and with each newly generated codeword, each previously stored code word is shifted to an adjacent row of the memory. In one example, the memory is delineated as a plurality of blocks including rows and columns of bits. When generating a new code word, randomly selected columns of bits in the memory are read from randomly selected blocks of the memory and supplied to the encoder. In this manner the number of times the memory is access is reduced and power consumption is reduced.