FEC Encoder Architecture Using 65-Bit Syndrome Generation
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Solution Overview
Problem
Conventional forward error correction (FEC) encoders in Ethernet systems suffer from latency and bulkiness due to input register delays and multi-cycle conversion processes, particularly with 66-bit and 65-bit bit lengths requiring 34-bit and 66-bit syndrome generators.
Innovation Solution
The proposed solution involves an encoder architecture with a 66-bit domain formatter interfacing with a 65-bit internal bus, simplifying the syndrome generator to use 65-bit syndrome generators, and a converter that concatenates data payload with parity bits, followed by scrambling with a pseudonoise sequence, to generate a 2112-bit frame efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 66-bit and 65-bit syndrome generators are used, then error correction capability is maintained, but device complexity and latency increase
Solution Approach 1:
The patent divides the encoding process into distinct stages: formatting 66-bit input words into 65-bit intermediate words, generating parity bits through syndrome calculation on the 65-bit words, and then reformatting into the final 66-bit codewords. This segmentation allows using smaller 65-bit syndrome generators instead of complex 66-bit generators, reducing device complexity while maintaining error correction capability.
Solution Approach 2:
The patent introduces 65-bit intermediate data words as a mediator between the 66-bit input data and the final 66-bit encoded output. These intermediate words serve as the basis for syndrome generation and parity bit calculation, enabling the use of simpler 65-bit syndrome generators while preserving the error correction functionality required for 66-bit data.
2Ease of operation
If input registers and multi-cycle conversion are used, then data alignment and formatting are achieved, but latency increases
Solution Approach 1:
The patent performs data formatting and alignment operations in advance during the formatting stage, where 66-bit input words are converted to 65-bit intermediate words with proper alignment before syndrome generation. This preliminary action ensures that the subsequent encoding stages can proceed without additional alignment delays, reducing overall latency.
Solution Approach 2:
The patent implements a continuous encoding pipeline where formatting, syndrome generation, and codeword assembly occur in an overlapping manner. While one set of data is being formatted, another set is undergoing syndrome generation, and previous data is being assembled into final codewords. This continuous operation eliminates idle cycles and reduces total encoding latency.
Data Source
AI summary
A method for encoding data words into a frame is provided. Input data words are received on a first bus having a first width. The input data words are buffered so as to output intermediate data words onto a second bus having a second width. A transcode bit is generated from the intermediate data words, and a set of parity bits is generated from the intermediate words using a syndrome generator, where the syndrome generator uses a number of bits that are equal to the second width. A frame is then generated from the intermediate data words and the set of parity bits and is output to a third bus having the first width.