FEC Encoding Scheme for Low-Latency High-Gain Serial Links
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Solution Overview
Problem
Existing FEC solutions in high-speed serial communication interfaces like PCIE and CCIX struggle to meet the requirements of low latency and high gain due to increasing link losses, which are exacerbated by larger chip packaging and higher data transfer rates, necessitating the use of forward error correction (FEC) that cannot satisfy both latency and gain requirements effectively.
Innovation Solution
An encoding method that generates FEC codewords with a valid information length as an integer multiple of the largest prime factor of the code block length, combined with error correction capability, allowing for efficient encoding that balances low latency and high error correction capability, using transcoding schemes like 128B/130B, 256B/257B, and 256B/258B to optimize FEC encoding for reduced overhead and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FEC encoding is introduced to compensate for link loss, then error correction capability is improved, but latency increases
Solution Approach 1:
The code block is divided into multiple sub-code blocks, each processed independently through FEC encoding. This segmentation allows parallel processing of multiple smaller units rather than waiting for a single large block, reducing overall encoding latency while maintaining comprehensive error correction coverage across the entire data stream
Solution Approach 2:
The patent applies FEC encoding to only a portion of the data stream at any given time by processing sub-code blocks sequentially or in parallel batches. This partial action approach provides sufficient error correction capability for the transmitted data while avoiding the need to encode the entire data stream before transmission begins, thereby reducing latency
2Reliability
If FEC encoding is introduced to compensate for link loss, then error correction capability is improved, but encoding overhead increases
Solution Approach 1:
By segmenting the code block into sub-code blocks and applying FEC encoding to each, the patent achieves comprehensive error correction with more efficient resource utilization. The segmented approach allows for optimized code rates and reduces the total overhead compared to applying a single large FEC code to the entire data stream
Solution Approach 2:
The patent dynamically adjusts FEC encoding parameters such as code rate, block size, and sub-code block division based on channel conditions and performance requirements. This parameter optimization enables the system to achieve the necessary error correction capability with minimal encoding overhead, adapting the overhead level to the actual link loss conditions
3Productivity
If chip packaging size increases to accommodate higher processing capabilities, then processing capability is improved, but packaging loss increases
Solution Approach 1:
The patent segments the data processing function across multiple smaller processing units within the chip packaging rather than requiring a single large processing unit. This segmentation reduces the physical packaging size required, thereby reducing packaging loss while maintaining or improving overall processing capability through parallel operation of the segmented units
Solution Approach 2:
The patent transitions from vertical stacking of processing functions to a more distributed, multi-dimensional architecture where processing units are arranged and interconnected in a way that reduces packaging density requirements. This dimensional reorganization allows higher processing capability with reduced packaging loss
4Productivity
If data transfer rate increases, then productivity is improved, but link loss increases
Solution Approach 1:
The patent dynamically adjusts FEC encoding parameters including code rate, block size, and sub-code block configuration based on the data transfer rate and corresponding link loss conditions. At higher transfer rates where link loss increases, the system adapts by increasing error correction capability while optimizing the balance between overhead and protection, thereby maintaining productivity while compensating for increased link loss
Data Source
AI summary
Embodiments of this application disclose an encoding method and a related device. The method includes: receiving a to-be-encoded code block whose length is L, where L is a positive integer; and encoding the to-be-encoded code block to obtain a forward error correction FEC code, where a valid information length K of the FEC code is an integer multiple of a largest prime factor of L, and a total length N of the FEC code is a sum of K and a product of 2 and an error correction capability T of the FEC code. According to the embodiments of this application, it can be ensured that an FEC codeword satisfies a requirement for a low latency and a high gain.