FEC Decoder Error Vector Packing for Bandwidth-Limited Reporting
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Solution Overview
Problem
Existing FEC decoders face significant bandwidth consumption issues due to the need to report error vectors of the same size as the codeword, which doubles the output bandwidth and is inefficient for resource utilization.
Innovation Solution
A circuit with an error vector packing mechanism that generates a summary vector of error information, including error values and locations, allowing for output in a size equal to or less than the parity symbols, thereby reducing bandwidth requirements and efficiently reporting errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the FEC decoder generates and reports a full error vector of the same size as the codeword, then complete error information is provided for analysis, but the output bandwidth doubles and resource efficiency deteriorates
Solution Approach 1:
The patent extracts only the essential error information (error values and locations) from the complete error vector, discarding redundant data. The error vector packing circuit identifies and outputs only the non-zero error symbols and their positions, rather than transmitting the entire error vector. This extraction principle reduces output bandwidth while preserving necessary error information for diagnostic and monitoring purposes.
Solution Approach 2:
The patent changes the representation parameters of error information by encoding error locations using logarithmic indexing (e.g., log2(N) bits for N-symbol codewords) and compressing error values to minimal required bit patterns. This parameter transformation converts the full-size error vector into a compact summary vector with significantly reduced bit width, resolving the bandwidth contradiction.
2Measurement precision
If the error vector size equals the codeword size, then all error positions are accurately identified, but the device complexity and resource utilization worsen
Solution Approach 1:
The patent segments the error vector into meaningful components: error location indices and error value magnitudes. The error vector packing circuit separates these elements and processes them independently, using segmentation to reduce the overall data structure size while maintaining precise error identification capabilities. This segmentation allows the decoder to handle error information in manageable parts rather than as a monolithic large structure.
Data Source
AI summary
A forward error correction decoder for packing error information of a codeword in the space that was previously occupied by the parity symbols in the decoder output is presented. Specifically, the decoder summarizes error information of the codeword in a summary vector having the size no greater than the total size of the parity symbols. The decoder then outputs the message symbols from the codeword and the summary error vector, which provides the error information of the received codeword but only requires a bandwidth that is no greater than the bandwidth previously used for transmitting the parity symbols.