FEC Entry Consolidation for FIB Memory Reduction

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Solution Overview

Problem

In datacenter environments with multiple virtual local area networks (VLANs), the forwarding information base (FIB) in multi-layer network elements consumes excessive memory due to the creation of multiple forwarding equivalence class (FEC) entries for each IP address, even if they resolve to the same egress port, leading to performance limitations.

Innovation Solution

A method to process routing entries in the FIB for directly attached hosts to encode Address Resolution Protocol (ARP) data into FEC entries, collapsing multiple exact match routing table entries into a single FEC entry per VLAN, thereby reducing memory consumption and FEC redundancy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple FEC entries are created for each IP address in the FIB, then forwarding precision and routing accuracy are improved, but memory consumption increases significantly

Engineering Contradiction:
Improverouting accuracyVSAvoidmemory consumption
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent merges multiple FEC entries that resolve to the same egress port into a single consolidated FEC entry. Instead of maintaining separate entries for each IP address within the same VLAN, the system consolidates them by grouping IP addresses under a common FEC identifier that maps to the shared egress port, thereby reducing memory consumption while preserving forwarding accuracy.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a universal FEC entry structure that can represent multiple IP addresses through a single entry. The FEC entry is designed to be multi-functional, serving as a common forwarding rule for all IP addresses within a VLAN that share the same egress port, eliminating the need for redundant individual entries.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If separate FEC entries are maintained for each IP address, then forwarding precision is improved, but device complexity increases

Engineering Contradiction:
Improveforwarding precisionVSAvoidFIB structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple individual FEC entries into a single consolidated entry by merging the forwarding rules for IP addresses that share the same egress port. This reduces the number of entries in the FIB from O(n) to O(1) per VLAN, where n is the number of IP addresses, thereby simplifying the FIB structure while maintaining precise forwarding capabilities.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a new dimensional approach to FIB organization by grouping entries along the VLAN dimension rather than the individual IP address dimension. This dimensional shift allows multiple IP addresses to be represented through a single FEC entry indexed by VLAN ID, reducing structural complexity while preserving forwarding precision.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If the FIB supports multiple VLANs with separate entries for each IP address, then network versatility is improved, but memory consumption increases

Engineering Contradiction:
ImproveVLAN support capabilityVSAvoidmemory usage
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent creates a universal FEC entry template that functions across all VLANs. Each FEC entry is designed to be VLAN-agnostic, allowing the same entry structure to serve multiple IP addresses within any VLAN that shares the same egress port. This multi-functional design enables full VLAN support while minimizing memory usage through consolidation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the representation of multiple VLANs and their associated IP addresses into a hierarchical structure where FEC entries are consolidated at the VLAN-egress port level. This merging approach allows the system to support numerous VLANs with their respective IP addresses while using a fraction of the memory that would be required for individual entries per IP address.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10530692B2Software FIB ARP FEC encoding
Publication Date: 2020.01.07 ARISTA NETWORKS INC
  • US10530692B2 patent drawing
  • US10530692B2 patent drawing
  • US10530692B2 patent drawing

AI summary

Described herein are various embodiments of a network element to process routing entries in a forwarding information base (FIB) for hosts that are directly attached to a multi-layer network element to encode address resolution protocol (ARP) data into forwarding equivalence class (FEC) entries for the directly attached hosts. One embodiment provides for a network element comprising a control plane including a forwarding agent and a data plane coupled to the control plane. The data plane can include a forwarding engine to forward a unit of network data from an ingress interface to an egress interface. The forwarding agent can be configured to program the forwarding engine with a forwarding information base having data-link layer forwarding data encoded into a network-layer forwarding entry.