FEC Frame Boundary Detection Using Iterative Data Block Parameters

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Solution Overview

Problem

Current methods for determining forward error correction (FEC) frame boundaries in high-speed communication links, such as those using Reed Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, are inefficient, often requiring excessive time and resources due to the need for redundant alignment markers or extensive data block checking.

Innovation Solution

A method and apparatus that determine FEC frame boundaries by analyzing parameter values of consecutive data blocks, using an iterative algorithm to identify frame boundaries within a reduced data set, thereby improving efficiency and reducing the time required to synchronize communication links.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If alignment markers are periodically added to data stream to determine FEC frame boundary, then frame boundary determination is simplified, but redundant information increases, circuit resources are consumed, and bit rate increases

Engineering Contradiction:
Improveframe boundary determinationVSAvoidredundant information
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent extracts and utilizes the inherent structure of FEC codes (specifically the properties of generator polynomials and check symbols) to identify frame boundaries, removing the need for separate alignment markers. The receiver extracts frame boundary information directly from the code structure itself rather than adding external markers.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The FEC code structure serves dual purposes: both error correction and frame boundary identification. The check symbols and generator polynomial properties that are already present for error protection also provide the means for frame synchronization, making the system self-sufficient without requiring additional alignment markers.

Inventive Principle:
Principle #25Self-service

2Ease of operation

If alignment markers are added to determine FEC frame boundary, then frame boundary detection is easier, but time interval between markers must be increased to control redundant information, resulting in longer determination time

Engineering Contradiction:
Improveframe boundary detectionVSAvoiddetermination time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The method extracts frame boundary information from every Nth symbol using the FEC code structure, providing continuous potential boundary candidates rather than relying on periodically inserted markers. This eliminates the trade-off between marker frequency and determination time.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The receiver performs preliminary validation checks (such as verifying check symbols or generator polynomial properties) on potential frame boundaries as data arrives, preparing and identifying valid boundaries in advance without waiting for periodic markers, thus reducing determination time.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If logic circuit searches data stream by checking N data blocks in worst case, then frame boundary can be found without alignment markers, but data of two-frame length must be received at each check, resulting in long determination time and low efficiency

Engineering Contradiction:
Improveredundant informationVSAvoiddetermination efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the frame boundary search into smaller validation steps. Instead of checking entire N-symbol blocks sequentially, it uses incremental validation methods such as checking check symbols or polynomial properties of smaller portions, allowing early termination when a valid boundary is found.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method performs partial validation checks on potential frame boundaries before committing to full frame processing. By checking only critical properties (such as check symbol validity or generator polynomial characteristics) rather than complete frame verification, it achieves faster boundary identification with reduced computational overhead.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3163779B1Method and apparatus for determining forward error correction frame boundary and decoding system
Publication Date: 2019.08.28 HUAWEI TECH CO LTD
  • EP3163779B1 patent drawingFigure 1
  • EP3163779B1 patent drawingFigure 2~3
  • EP3163779B1 patent drawingFigure 4~5

AI summary

The present invention provides a method and an apparatus for determining a frame boundary of an FEC frame, and a decoding system, which are mainly applicable to an RS code and a BCH code. The method includes: receiving data, where the data includes N+P consecutive symbols with a first symbol being a starting point, N consecutive symbols with the first symbol being a starting point that are in the N+P consecutive symbols constitute a first data block, and N consecutive symbols with a second symbol being a starting point that are in the N+P consecutive symbols constitute a second data block; obtaining s parameter values corresponding to the first data block; determining a first iterative item and a second iterative item of the second data block; determining, according to the s parameter values corresponding to the first data block and the first iterative item and the second iterative item of the second data block, s parameter values corresponding to the second data block; and determining, according to the s parameter values corresponding to the second data block, whether the second symbol is a frame boundary of an FEC frame. The method for determining a frame boundary of an FEC frame disclosed in the present invention can improve efficiency of detecting a frame boundary of an FEC frame.