Forward Error Correction Frame Scheduling for Throughput Optimization
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Solution Overview
Problem
Current Forward Error Correction (FEC) devices in satellite communication networks, particularly those using the DVB-S2 standard, face challenges in achieving high throughput due to limitations in processing capacity and power consumption, leading to issues with media content delivery such as buffering and synchronization problems.
Innovation Solution
A system and method that employs a controller to evaluate and arrange frames with different modulation and coding characteristics in an alternating order within a transmission window, enabling efficient iteration borrowing and improving FEC processing efficiency by allocating processing time from frames that require fewer iterations to those that need more, thereby enhancing FEC frame error rate performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the complexity of the FEC device subsystem is increased by adding more processing engines, then the throughput of the FEC device is improved, but the die area and device cost increase
Solution Approach 1:
The patent applies dynamic processing by varying the number of iteration loops executed by the FEC processing engines based on the specific frame being processed. Frames with better signal quality require fewer iterations while frames with poorer quality require more iterations. This dynamic adaptation allows the system to achieve high throughput without adding more processing engines, as the existing engines are utilized more efficiently with variable iteration counts rather than fixed maximum iterations for all frames.
2Productivity
If the operating clock speed of the FEC device subsystem is increased, then the throughput of the FEC device is improved, but timing margins and power consumption are constrained
Solution Approach 1:
The system dynamically adjusts the processing effort for each frame by varying the number of iteration loops based on signal quality metrics. This allows the FEC device to maintain higher throughput without continuously operating at maximum clock speed, thereby reducing average power consumption. The processing engines operate at a moderate clock speed but intensify effort selectively for difficult frames rather than maintaining high speed for all frames.
Solution Approach 2:
The patent changes the processing parameter (number of iteration loops) based on the quality of each received frame. Frames with higher signal-to-noise ratios use fewer iterations while frames with lower quality use more iterations. This parameter adaptation allows the system to achieve high overall throughput without the need to increase clock speed across all operations, thus avoiding the associated power consumption increases and timing margin issues.
3Productivity
If the operating clock speed of the FEC device subsystem is increased, then the throughput of the FEC device is improved, but timing margins are constrained
Solution Approach 1:
The system uses dynamic iteration counting where the number of processing loops varies per frame based on quality metrics. This allows the FEC device to complete processing of most frames within the allocated time window without requiring excessive clock speed increases. By adapting the processing depth to actual needs, the system maintains timing margins for variable-length processing while achieving high throughput, avoiding the timing closure issues that would result from uniformly high clock speeds.
Data Source
AI summary
A system and method for improving forward error correction efficiency in a communication network. The system and method employ a controller configured to evaluate a plurality of frames to identify a first type of the plurality of frames having a first frame processing characteristic pertaining to a first type of frame iteration processing performed by a terminal of the communication network and a second type of the plurality of frames having a second frame processing characteristic pertaining to a second type of frame iteration processing performed by the terminal. The controller is further configured to arrange a plurality of the first type of frames and at least one of the plurality of the second type of frames in an alternating order within a transmission window for transmission to the terminal.