FEC Idle-State Control for Low-Latency Network Power Saving
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Solution Overview
Problem
Conventional network devices, such as switches, waste significant power during periods of low traffic due to high entry and exit latencies in existing power-saving approaches, which are not optimized for modern computing environments with varying traffic demands.
Innovation Solution
A system and method that disable Forward Error Correction (FEC) encoder and decoder functionalities during link idle periods, synchronized across partner nodes to minimize entry and exit latencies, using a vendor-specific header for secure control information transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If L1 power saving approaches are used to save power during idle periods, then power consumption is reduced, but entry and exit latencies increase significantly (on the order of 100 us)
Solution Approach 1:
The patent implements dynamic power management by transitioning FEC encoder/decoder circuits between active and idle states based on real-time link traffic conditions. The system dynamically adjusts power consumption of encoding/decoding operations without fully powering down the communication link, achieving a balance between power savings and latency performance.
Solution Approach 2:
The patent changes the operational state parameter of FEC encoder/decoder circuits from fully active to a low-power idle state during link idle periods. By modifying the power state parameter of these specific components while maintaining link connectivity, the system achieves power savings with minimal latency impact compared to complete link shutdown approaches.
2Loss of energy
If FEC encoder and decoder functionalities are disabled during link idle periods, then power consumption is reduced, but communication reliability may be compromised
Solution Approach 1:
The patent enables partner nodes to synchronize their FEC encoder/decoder state transitions in advance before actual data transmission begins. By performing preliminary synchronization during the idle state transition, the system ensures both ends are ready to resume error correction operations immediately when traffic starts, maintaining reliability without sacrificing power savings.
Solution Approach 2:
The patent implements a feedback mechanism where partner nodes exchange synchronization information regarding their FEC encoder/decoder states. This feedback ensures both ends of the communication link are aware of each other's power state, preventing data loss or errors during state transitions while maintaining the power-saving benefits of disabled FEC operations during idle periods.
Data Source
AI summary
A device or system including one or more devices is provided. In one example, a device includes one or more circuits that enable the device to determine that a communication link between a first communication node and a second communication node is in a link idle state. The device may further, in response to determining that the communication link is in the link idle state, transmit a disable command to one or both of the first communication node and the second communication node, where the disable command causes a recipient thereof to disable part of an encoding operation for the communication link.