FEC Interleaving Alignment for Low-Latency Codeword Mapping

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Solution Overview

Problem

Current concatenated FEC-based transmission solutions suffer from high latency due to convolutional interleaving, which is not ideal for scenarios requiring low latency.

Innovation Solution

Implement interleaving alignment before convolutional interleaving, using delay lines with varying storage units to map outer-code codewords to inner-code codewords with minimal interleaving delay, and perform second FEC encoding to optimize concatenated code performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If convolutional interleaving is performed to achieve good transmission performance, then reliability is improved, but latency increases

Engineering Contradiction:
Improvetransmission performanceVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the convolutional interleaving process into multiple parallel sub-interleavers, each handling a portion of the data stream. By dividing the single long-latency interleaving operation into multiple shorter parallel operations, the system achieves the same error dispersion performance with reduced latency in each path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic delay adjustment mechanisms that allow the interleaving depth and delay characteristics to be adapted based on channel conditions and performance requirements. This enables optimization between latency and reliability by dynamically adjusting the interleaving parameters rather than using fixed deep interleaving.

Inventive Principle:
Principle #15Dynamics

2Reliability

If deep convolutional interleaving is used to improve concatenated code performance, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveconcatenated code performanceVSAvoidinterleaving structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the complex deep convolutional interleaving into multiple simpler parallel sub-interleavers with smaller memory requirements. Each sub-interleaver handles a segment of the codeword with reduced complexity, while collectively achieving the performance of a single deep interleaver.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple parallel interleaving paths with different delay characteristics to achieve the equivalent effect of a single complex interleaver. By merging the outputs of simpler parallel structures, the system achieves deep interleaving performance without the complexity of a single large-scale interleaving device.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20260031928A1Data Processing Method and Data Processing Apparatus
Publication Date: 2026.01.29 HUAWEI TECH CO LTD
  • US20260031928A1 patent drawing
  • US20260031928A1 patent drawing
  • US20260031928A1 patent drawing

AI summary

A data processing method includes, for a concatenated FEC-based transmission solution, interleaving alignment that is first performed before convolutional interleaving is performed on a first data stream, to determine a boundary of each bit set in the first data stream and a boundary of each bit subset in the bit set. Further, bit subsets are sent as a granularity to each storage unit in a convolutional interleaving operation. Each bit subset includes d bits, and each storage unit is configured to store d bits. The bits in each bit subset are from v symbols, and the v symbols are respectively from v first codewords. One symbol is selected from each of the v first codewords to form a bit subset.