Concatenated FEC Interleaving Alignment for Low-Latency Transmission

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Solution Overview

Problem

Current concatenated FEC-based transmission solutions suffer from high latency, which is not ideal for scenarios requiring low latency.

Innovation Solution

A data processing method involving interleaving alignment before convolutional interleaving, where bit subsets are sent as a granularity to storage units, and subsequent convolutional interleaving is performed to minimize latency while maintaining good performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If convolutional interleaving is performed with long latency to achieve good performance, then the error correction performance is improved, but the transmission latency increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidtransmission latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the data stream into multiple lanes and performs parallel convolutional interleaving on each lane independently. By dividing the original single-stream processing into m parallel lanes, the system reduces the effective interleaving depth required per lane while maintaining overall error correction performance, thus lowering latency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the interleaving parameters for each lane based on the specific transmission scenario requirements. Different lanes can have different interleaving depths and patterns, allowing the system to optimize the balance between error correction performance and latency dynamically rather than using a fixed conservative configuration.

Inventive Principle:
Principle #15Dynamics

2Reliability

If concatenated FEC encoding is performed with multiple encoding stages, then the error correction capability is improved, but the processing complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the concatenated FEC processing into separate parallel lanes, where each lane undergoes independent convolutional interleaving and FEC encoding. This segmentation allows each processing stage to operate on smaller data units in parallel, reducing the complexity of individual stages while maintaining the benefits of concatenated coding through the combination of multiple lanes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs convolutional interleaving as a preliminary action before the main FEC encoding process. By pre-organizing the data in each lane through interleaving, the subsequent FEC encoding operates on already-optimized data structures, reducing the computational complexity of the encoding process while maintaining error correction capability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4672616A1Data processing method and data processing apparatus
Publication Date: 2025.12.31 HUAWEI CLOUD COMPUTING TECHNOLOGIES CO LTD
  • EP4672616A1 patent drawingFigure 1
  • EP4672616A1 patent drawingFigure 2
  • EP4672616A1 patent drawingFigure 3

AI summary

Embodiments of this application disclose a data processing method and a data processing apparatus, so that good performance of a concatenated FEC-based solution can be achieved in a scenario with a low latency. For a concatenated FEC-based transmission solution, interleaving alignment needs to be first performed before convolutional interleaving is performed on a first data stream, to determine a boundary of each bit set in the first data stream and a boundary of each bit subset in the bit set. Further, bit subsets are sent as a granularity to each storage unit in a convolutional interleaving operation. In other words, each bit subset includes d bits, and each storage unit is configured to store d bits. The bits in each bit subset are from v symbols, and the v symbols are respectively from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.