Concatenated FEC Interleaving for Low-Latency Optical Transmission
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Solution Overview
Problem
Optical transmission systems face challenges in achieving high throughput with low latency and reduced circuit size due to the need for large-capacity memories in interleaving and deinterleaving processes for error correction coding.
Innovation Solution
A transmission device employing an outer code interleaver, outer coding unit, outer code deinterleaver, inner coding unit, and inner code interleaver to perform error correction coding with interleaving and deinterleaving without the use of memory, using concatenated error correction codes for multilevel modulation symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large-capacity memories are used for interleaving and deinterleaving processes in error correction coding, then error correction performance is improved, but device complexity and circuit size increase
Solution Approach 1:
The patent divides the error correction coding system into outer code and inner code components, each with their own interleaving and deinterleaving processes. This segmentation allows the use of smaller, more manageable memory units distributed across multiple coding circuits rather than requiring a single large memory, thereby reducing overall circuit complexity while maintaining error correction performance
Solution Approach 2:
The patent introduces time interleaving as an additional dimension to the traditional space-based interleaving approach. By distributing data across time slots in addition to spatial positions, the system achieves effective error correction without requiring proportionally larger memory capacity, thus resolving the contradiction between reliability and device complexity
2Reliability
If large-capacity memories are used for interleaving and deinterleaving processes, then error correction capability is enhanced, but transmission latency increases
Solution Approach 1:
By segmenting the error correction process into outer and inner codes with separate interleaving stages, the patent enables parallel processing of multiple data streams. This segmentation reduces the amount of data that needs to be stored and processed sequentially in memory, thereby decreasing transmission latency while preserving error correction capability
Solution Approach 2:
The outer code interleaving is performed preliminarily before the main error correction coding process. This preliminary action distributes potential burst errors across multiple code blocks in advance, allowing the subsequent inner code to correct errors more efficiently with smaller memory requirements and reduced processing delay
3Productivity
If multiple error correction coding circuits are used to achieve high transmission capacity, then transmission capacity is improved, but device complexity increases
Solution Approach 1:
The patent designs the outer code interleaver and deinterleaver to handle multiple data streams simultaneously, making these components multi-functional. This universality allows a single interleaving structure to support multiple parallel coding circuits, thereby increasing transmission capacity without proportionally increasing overall device complexity
Solution Approach 2:
The patent employs time interleaving that operates across multiple coding circuits in parallel, adding a temporal dimension to the processing architecture. This approach enables high transmission capacity through parallel processing while keeping each individual circuit relatively simple, as the complexity is distributed across time and multiple identical modules rather than concentrated in a single complex circuit
Data Source
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AI summary
A transmission device (100) includes an outer code interleaver (1) that generates multiple bit sequences while performing interleaving on a signal formed of multiple multilevel modulation symbols on a per-bit basis, an outer coding unit (2) that performs outer coding processings, in parallel, on the multiple respective bit sequences generated by the interleaving, an outer code deinterleaver (3) that performs deinterleaving on bit sequences obtained by performing the outer coding processings, the deinterleaving being inverse operation of the interleaving performed by the outer code interleaver, an inner coding unit (4) that performs inner coding processings, in parallel, on bit sequences obtained by performing the deinterleaving in the outer code deinterleaver, and an inner code interleaver (5) that performs time interleaving and symbol interleaving on bit sequences obtained by performing the inner coding processings.