FEC Decoding Pipeline for RS-BCH Intersection Error Recovery
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Solution Overview
Problem
In high-speed communication systems, errors in data transmission often exceed the correction capabilities of standard Reed-Solomon (RS) and BCH error correction codes, leading to uncorrectable errors at the intersection of RS and BCH words, where neither decoding algorithm can recover bits in error.
Innovation Solution
A decoding pipeline with multiple stages is implemented, including BCH and RS decoders, along with a post-processing circuit that performs bitwise RS decoding on error-indicating words, using syndrome expansion and inverse matrix multiplication to correct errors beyond the capability of individual codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard RS and BCH error correction codes are used, then the correction capability is sufficient for normal transmission conditions, but errors at the intersection of RS and BCH words cannot be corrected when transmission quality degrades severely
Solution Approach 1:
The patent segments the error correction process into multiple stages: first RS decoding, then BCH decoding, and finally a post-processing stage that handles intersection errors. This segmentation allows each decoder to operate within its optimal capability range while the post-processing stage addresses the specific problem of intersection errors that neither decoder can handle alone.
Solution Approach 2:
The patent introduces a post-processing circuit as an intermediary between the RS and BCH decoders. This intermediary component performs bitwise RS decoding on syndromes generated by the BCH decoder, acting as a mediator that resolves the intersection error problem by combining information from both decoding processes.
2Reliability
If more powerful FEC codes are used to correct more errors, then the correction capability increases, but the complexity of the decoding process increases
Solution Approach 1:
The patent applies partial action by implementing a post-processing circuit that only activates when specific conditions are met (when BCH decoding fails to correct intersection errors). Instead of always performing full bitwise RS decoding on all data, the system selectively applies additional decoding only where needed, balancing complexity and correction capability.
Solution Approach 2:
The patent applies local quality by focusing the post-processing effort specifically on intersection errors between RS and BCH words, rather than attempting to correct all possible errors uniformly. The post-processing circuit targets the specific location and type of errors that arise at the intersection, applying bitwise RS decoding only to the affected syndromes.
3Reliability
If iterative decoding between BCH and RS is performed, then more errors can be recovered, but the decoding time increases
Solution Approach 1:
The patent performs preliminary action by first attempting standard RS decoding and then BCH decoding before invoking the post-processing circuit. This preliminary decoding sequence allows the system to correct many errors quickly using standard algorithms, reserving the more time-consuming post-processing for only those cases where intersection errors persist.
Solution Approach 2:
The patent implements skipping by allowing the iterative decoding process to proceed through standard RS and BCH decoding stages without interruption, and only invoking the post-processing circuit when necessary. This approach rushes through the common case of correctable errors using fast algorithms, while skipping directly to detailed post-processing only when intersection errors are detected.
Data Source
AI summary
A decoding circuit is disclosed that includes a decoding pipeline configured to receive a data block that includes a plurality of data symbols, encoded with a Reed-Solomon (RS) FEC coding thereafter further encoded by a second FEC coding. The data block also includes a first and second sets of FEC datagrams for correcting received words of the plurality of data symbols encoded with the RS FEC coding and second FEC coding, respectively. Each decoding stage of the pipeline is configured to decode the plurality of data symbols using the first and second sets of FEC datagrams. A post-processing circuit connected to an output of the pipelines is configured to perform bitwise RS decoding of ones of the plurality of data symbols in error.