FEC Decoder Processor Scheduling for Power-Stable Throughput
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Solution Overview
Problem
Existing methods for decoding forward error correction (FEC) codewords in transceivers are inefficient in managing processor activation and deactivation, leading to unnecessary power consumption and suboptimal performance.
Innovation Solution
A method and apparatus for scheduling and operating processors that dynamically adjust the activation and deactivation of processors based on the rate of increment or decrement, using thresholds and low pass filtering to optimize power usage and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If processors are dynamically activated and deactivated for decoding FEC codewords, then power consumption is reduced, but decoding performance and reliability deteriorate
Solution Approach 1:
The system dynamically adjusts the number of active processors based on the decoding progress and requirements of FEC codewords. The scheduler monitors iteration counts and performance metrics, activating additional processors when decoding difficulty increases and deactivating processors when decoding converges, thereby optimizing the balance between power consumption and decoding reliability
Solution Approach 2:
The system implements feedback mechanisms where the scheduler continuously monitors decoding performance metrics such as iteration counts and error correction success rates. Based on this feedback, the scheduler makes informed decisions about processor activation and deactivation, ensuring that decoding reliability is maintained while minimizing power consumption
2Productivity
If the number of active processors is increased for faster decoding, then productivity improves, but power consumption increases
Solution Approach 1:
The system applies partial action by activating only the necessary number of processors required for current decoding workload rather than keeping all processors active. The scheduler assesses the decoding complexity of incoming FEC codewords and activates a corresponding subset of processors, avoiding the excessive power consumption that would result from keeping all processors active regardless of actual need
3Loss of energy
If processors are frequently activated and deactivated to optimize power usage, then energy efficiency improves, but system stability deteriorates
Solution Approach 1:
The system implements prior cushioning by maintaining a buffer of recently deactivated processors in a low-power standby state rather than fully powering them down. This allows for rapid reactivation if decoding workload suddenly increases, cushioning against potential system instability while still achieving energy efficiency during low-load periods
Data Source
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AI summary
An apparatus for and a method of operating processors (108) for decoding forward error correction, FEC, codewords, wherein the method comprises determining a rate of an increment in processors (108) that are active for decoding FEC codewords, and inhibiting (116) activation of a processor (108) for decoding FEC codewords when the rate of the increment is larger than a first threshold. An apparatus for and a method of scheduling processors (108) for decoding forward error correction, FEC, codewords, wherein the method comprises receiving an indication (116) to inhibit activation of a processor (108) for decoding FEC codewords, and to inhibit activation of a processor (108) for decoding FEC codewords upon receiving the indication (116) to inhibit activation of a processor (108), or receiving an indication to inhibit deactivation of a processor (108) for decoding FEC codewords, and to inhibit deactivation of a processor (108) for decoding FEC codewords upon receiving the indication to inhibit deactivation of a processor (108).