FEC Schedule Representation for Parallel Encoding and Decoding
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Solution Overview
Problem
Existing communication systems face challenges in efficiently encoding and decoding data to correct errors and erasures in data transmission, especially in adverse environments or when reverse channels are not available, leading to unreliable data recovery.
Innovation Solution
A method and apparatus for representing schedules of symbol operations to direct the processing of forward error correction (FEC) codes in a computationally efficient manner, allowing for efficient encoding and decoding of data by segmenting blocks, using parallel processing, and reducing computational complexity through the use of Hamming weights and inactive symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional FEC encoding and decoding methods are used, then data recovery reliability is improved, but computational complexity and resource requirements increase
Solution Approach 1:
The patent segments the data block into multiple sub-blocks and processes each sub-block independently through parallel decoding operations. This division reduces the computational complexity of handling large data blocks while maintaining overall data recovery reliability through the coordinated processing of segments.
Solution Approach 2:
The patent pre-computes and stores schedules of symbol operations that direct the processing of FEC codes. By preparing these operation schedules in advance, the system reduces real-time computational complexity during actual encoding and decoding operations while ensuring reliable data recovery.
2Reliability
If comprehensive FEC processing is performed on entire data blocks, then error correction capability is improved, but memory requirements and processing time increase
Solution Approach 1:
The patent divides the data block into smaller sub-blocks that can be processed concurrently. This segmentation enables parallel decoding operations across multiple sub-blocks, significantly reducing the overall processing time while maintaining error correction capability through the collective processing of all segments.
Solution Approach 2:
The patent implements continuous parallel processing of multiple sub-blocks simultaneously rather than sequential processing. This continuous useful action across parallel streams reduces total processing time while maintaining comprehensive error correction through the coordinated completion of all sub-block processing.
3Reliability
If systematic FEC encoding is used, then data integrity is improved, but computational resources and complexity increase
Solution Approach 1:
The patent pre-computes systematic FEC encoding schedules and stores them for reuse. By performing the computationally intensive schedule generation in advance, the system reduces real-time computational resource consumption during actual encoding operations while maintaining data integrity through the application of pre-validated encoding schedules.
Solution Approach 2:
The patent segments the systematic encoding process into independent sub-block operations that can be executed with reduced computational resources. Each sub-block is encoded using pre-computed schedules, reducing the instantaneous computational burden while maintaining overall data integrity through the systematic processing of all segments.
Data Source
AI summary
A sequence of symbol operations (a “schedule representation”) within a data storage device, wherein the operations are those used to process encoding or decoding operations of a forward error correction code (an “FEC code”) upon an arbitrary block of data of a given size (where size can be measured in numbers of symbols). The method is such that the schedule representation can be used to direct the processing of these operations upon a block of data in a way that is computationally efficient. Preferably, the same method can be applied to represent schedules derived from multiple different algorithms for the encoding or decoding of a code or for multiple different codes.