Error Rate Measuring Apparatus FEC Symbol Error Visualization
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Solution Overview
Problem
Existing error rate measuring apparatuses cannot effectively recognize the occurrence of errors by each FEC symbol length, making it difficult to diagnose and debug devices under test, especially when errors occur due to specific input patterns and when forward error correction is impossible.
Innovation Solution
An error rate measuring apparatus that inputs either an NRZ or PAM4 signal as a test signal to a device under test, measures the bit error rate, and uses data comparison units to detect FEC symbol errors by setting codeword and FEC symbol lengths corresponding to the device's communication standard, with a display unit performing color-coding to visually represent error occurrences by each FEC symbol length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bit error position display is implemented, then bit error location can be shown, but FEC symbol error recognition by each FEC symbol length is not possible
Solution Approach 1:
The patent divides the bit error data into segments corresponding to each FEC symbol length. The error position display unit is configured to display errors segmented by FEC symbol boundaries, allowing simultaneous visualization of both bit-level precision and FEC symbol-level grouping. This segmentation enables users to see which FEC symbols contain errors while maintaining the detailed bit position information within each symbol.
Solution Approach 2:
The patent adds a new dimension to the error display by organizing error information in a two-dimensional structure: one dimension represents the bit position within an FEC symbol, and the other dimension represents the FEC symbol sequence. This dimensional transformation allows the display to simultaneously show bit-level precision and FEC symbol-level patterns without losing either type of information.
2Ease of operation
If detailed bit error information is displayed, then bit-level debugging is enabled, but efficient FEC symbol-level debugging is not achieved
Solution Approach 1:
The display system segments error information into hierarchical levels: FEC symbol level and bit level within each symbol. This segmentation allows debuggers to quickly identify which FEC symbols contain errors at the symbol level, then drill down to specific bit positions within those symbols, making the debugging process more efficient by reducing the search space.
Solution Approach 2:
The patent introduces an intermediary display structure that acts as a bridge between bit-level error data and FEC symbol-level analysis. This intermediary organization groups bit errors by their corresponding FEC symbols, providing a intermediate view that facilitates both detailed bit-level inspection and efficient symbol-level pattern recognition.
3Device complexity
If error distribution by FEC symbol length is not provided, then device complexity is reduced, but debugging capability is insufficient
Solution Approach 1:
The patent implements segmentation of error display by FEC symbol length using a straightforward grouping method that divides bit error positions into segments corresponding to each FEC symbol. This segmentation approach adds minimal complexity to the display system while significantly improving error detection capability, as it naturally organizes data into meaningful FEC symbol groups without requiring complex processing.
Solution Approach 2:
The display system creates a copied and reorganized version of the bit error data, where errors are replicated and grouped according to their FEC symbol assignments. This copying approach allows the original bit-level information to be preserved while simultaneously presenting a FEC symbol-level view, enhancing detection capability without substantially increasing system complexity.
Data Source
AI summary
An error rate measuring apparatus that measures whether or not an FEC operation of the device under test is possible based on a comparison result of the signal received from the device under test and a test signal includes an operation unit that sets a codeword length and an FEC symbol length of the FEC corresponding to a communication standard of the device under test, a data comparison unit that compares bit string data obtained by converting the signal received from the device under test with error data to detect an FEC symbol error of each FEC symbol length, a display unit that associates the bit string data of the FEC symbol length as one point with one unit region of a display region and performs color-coding display depending on presence or absence of occurrence of the FEC symbol error by each FEC symbol length.